Lines Matching defs:NOR
964 unsigned LL, SC, AND, NOR, ZERO, BEQ;
975 NOR = Mips::NOR;
982 NOR = Mips::NOR64;
1025 // nor storeval, $0, andres
1027 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1134 // nor mask2,$0,mask
1155 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1181 // nor binopres, $0, andres
1184 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1372 // nor mask2,$0,mask
1395 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
2031 // Return if load is aligned or if MemVT is neither i32 nor i64.
