Lines Matching defs:ShiftAmt
1089 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1131 // sll shiftamt,ptrlsb2,3
1133 // sll mask,maskupper,shiftamt
1135 // sll incr2,incr,shiftamt
1144 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1149 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1154 .addReg(MaskUpper).addReg(ShiftAmt);
1156 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1208 // srl srlres,maskedoldval1,shiftamt
1215 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1322 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1369 // sll shiftamt,ptrlsb2,3
1371 // sll mask,maskupper,shiftamt
1374 // sll shiftedcmpval,maskedcmpval,shiftamt
1376 // sll shiftednewval,maskednewval,shiftamt
1384 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1389 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1394 .addReg(MaskUpper).addReg(ShiftAmt);
1399 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1403 .addReg(MaskedNewVal).addReg(ShiftAmt);
1432 // srl srlres,maskedoldval0,shiftamt
1437 .addReg(MaskedOldVal0).addReg(ShiftAmt);
