Lines Matching full:mips
16 #include "Mips.h"
32 #define DEBUG_TYPE "mips-long-branch"
37 "skip-mips-long-branch",
39 cl::desc("MIPS: Skip long branch pass."),
43 "force-mips-long-branch",
45 cl::desc("MIPS: Expand all branches to long format."),
72 return "Mips Long Branch";
274 unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR;
293 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
294 .addReg(Mips::SP).addImm(-8);
295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
296 .addReg(Mips::SP).addImm(0);
314 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
318 .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
319 .addReg(Mips::AT)
325 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
326 .addReg(Mips::RA).addReg(Mips::AT);
327 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
328 .addReg(Mips::SP).addImm(0);
332 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
333 .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP)
334 .addReg(Mips::SP).addImm(8));
337 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
338 .addReg(Mips::SP).addImm(8);
341 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
342 .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
380 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
381 .addReg(Mips::SP_64).addImm(-16);
382 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64)
383 .addReg(Mips::SP_64).addImm(0);
384 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
385 Mips::AT_64).addReg(Mips::ZERO_64)
387 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
388 .addReg(Mips::AT_64).addImm(16);
393 BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)
394 .addReg(Mips::AT_64)
400 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
401 .addReg(Mips::RA_64).addReg(Mips::AT_64);
402 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
403 .addReg(Mips::SP_64).addImm(0);
406 .append(BuildMI(*MF, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64))
407 .append(BuildMI(*MF, DL, TII->get(Mips::DADDiu), Mips::SP_64)
408 .addReg(Mips::SP_64).addImm(16));
421 .append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
422 .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
441 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
443 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
444 .addReg(Mips::V0).addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
445 MBB.removeLiveIn(Mips::V0);
