Lines Matching full:mips
1 //===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
11 // Declarations that describe the MIPS register file
13 let Namespace = "Mips" in {
32 let Namespace = "Mips";
38 let Namespace = "Mips";
41 // Mips CPU Registers
44 // Mips 64-bit CPU Registers
50 // Mips 32-bit FPU Registers
53 // Mips 64-bit (aliased) FPU Registers
66 // Mips 128-bit (aliased) MSA Registers
79 // Mips Hardware Registers
86 let Namespace = "Mips" in {
155 /// Mips Single point precision FPU Registers
163 /// Mips Double point precision FPU Registers (aliased
170 /// Mips Double point precision FPU Registers in MFP64 mode.
175 /// Mips MSA registers
269 RegisterClass<"Mips", regTypes, 32, (add
286 def GPR64 : RegisterClass<"Mips", [i64], 64, (add
300 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
306 def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add
313 def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
315 def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
324 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
326 def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>,
329 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
341 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
344 def OddSP : RegisterClass<"Mips", [f32], 32,
350 def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
354 def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
359 def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>;
361 def MSA128B: RegisterClass<"Mips", [v16i8], 128,
363 def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
365 def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128,
367 def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128,
370 def MSACtrl: RegisterClass<"Mips", [i32], 32, (add
374 def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;
375 def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>;
376 def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>;
377 def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>;
378 def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>;
379 def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>;
382 def HWRegs : RegisterClass<"Mips", [i32], 32, (sequence "HWR%u", 0, 31)>,
386 def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
390 def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
394 def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
398 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
401 def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>,
405 def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>,
409 def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>,
411 def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>,
