Lines Matching full:mips
16 #include "Mips.h"
37 #define DEBUG_TYPE "mips-isel"
52 MIB.addReg(Mips::DSPPos, Flag);
55 MIB.addReg(Mips::DSPSCount, Flag);
58 MIB.addReg(Mips::DSPCarry, Flag);
61 MIB.addReg(Mips::DSPOutFlag, Flag);
64 MIB.addReg(Mips::DSPCCond, Flag);
67 MIB.addReg(Mips::DSPEFI, Flag);
74 case 0: return Mips::MSAIR;
75 case 1: return Mips::MSACSR;
76 case 2: return Mips::MSAAccess;
77 case 3: return Mips::MSASave;
78 case 4: return Mips::MSAModify;
79 case 5: return Mips::MSARequest;
80 case 6: return Mips::MSAMap;
81 case 7: return Mips::MSAUnmap;
90 if ((MI.getOpcode() == Mips::ADDiu) &&
91 (MI.getOperand(1).getReg() == Mips::ZERO) &&
94 ZeroReg = Mips::ZERO;
95 } else if ((MI.getOpcode() == Mips::DADDiu) &&
96 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
99 ZeroReg = Mips::ZERO_64;
138 RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
140 RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
146 MF.getRegInfo().addLiveIn(Mips::T9_64);
147 MBB.addLiveIn(Mips::T9_64);
153 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
155 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
156 .addReg(Mips::T9_64);
157 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
167 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
169 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
174 MF.getRegInfo().addLiveIn(Mips::T9);
175 MBB.addLiveIn(Mips::T9);
182 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
184 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
185 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
206 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
209 MF.getRegInfo().addLiveIn(Mips::V0);
210 MBB.addLiveIn(Mips::V0);
211 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
212 .addReg(Mips::V0).addReg(Mips::T9);
223 if (I->getOpcode() == Mips::RDDSP)
225 else if (I->getOpcode() == Mips::WRDSP)
245 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
246 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
289 /// Used on Mips Load/Store instructions
339 /// Used on Mips Load/Store instructions
646 Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
654 Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
663 Mips::ZERO_64, MVT::i64);
664 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
667 Mips::ZERO, MVT::i32);
668 Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
672 Mips::ZERO, MVT::i32);
673 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
704 if (Inst->Opc == Mips::LUi64)
709 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
748 CurDAG->getMachineNode(Mips::MOVE_V, DL,
777 RdhwrOpc = Mips::RDHWR;
778 DestReg = Mips::V1;
780 RdhwrOpc = Mips::RDHWR64;
781 DestReg = Mips::V1_64;
787 CurDAG->getRegister(Mips::HWR29, MVT::i32));
828 LdiOp = Mips::LDI_B;
832 LdiOp = Mips::LDI_H;
836 LdiOp = Mips::LDI_W;
840 LdiOp = Mips::LDI_D;
861 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
