Lines Matching full:mips
29 tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
47 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
48 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
70 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
71 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
89 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
90 if (Mips::GPR32RegClass.contains(SrcReg)) {
92 Opc = Mips::MOVE16_MM;
94 Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
95 } else if (Mips::CCRRegClass.contains(SrcReg))
96 Opc = Mips::CFC1;
97 else if (Mips::FGR32RegClass.contains(SrcReg))
98 Opc = Mips::MFC1;
99 else if (Mips::HI32RegClass.contains(SrcReg)) {
100 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
102 } else if (Mips::LO32RegClass.contains(SrcReg)) {
103 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
105 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
106 Opc = Mips::MFHI_DSP;
107 else if (Mips::LO32DSPRegClass.contains(SrcReg))
108 Opc = Mips::MFLO_DSP;
109 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
110 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
114 else if (Mips::MSACtrlRegClass.contains(SrcReg))
115 Opc = Mips::CFCMSA;
117 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
118 if (Mips::CCRRegClass.contains(DestReg))
119 Opc = Mips::CTC1;
120 else if (Mips::FGR32RegClass.contains(DestReg))
121 Opc = Mips::MTC1;
122 else if (Mips::HI32RegClass.contains(DestReg))
123 Opc = Mips::MTHI, DestReg = 0;
124 else if (Mips::LO32RegClass.contains(DestReg))
125 Opc = Mips::MTLO, DestReg = 0;
126 else if (Mips::HI32DSPRegClass.contains(DestReg))
127 Opc = Mips::MTHI_DSP;
128 else if (Mips::LO32DSPRegClass.contains(DestReg))
129 Opc = Mips::MTLO_DSP;
130 else if (Mips::DSPCCRegClass.contains(DestReg)) {
131 BuildMI(MBB, I, DL, get(Mips::WRDSP))
136 else if (Mips::MSACtrlRegClass.contains(DestReg))
137 Opc = Mips::CTCMSA;
139 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
140 Opc = Mips::FMOV_S;
141 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
142 Opc = Mips::FMOV_D32;
143 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
144 Opc = Mips::FMOV_D64;
145 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
146 if (Mips::GPR64RegClass.contains(SrcReg))
147 Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
148 else if (Mips::HI64RegClass.contains(SrcReg))
149 Opc = Mips::MFHI64, SrcReg = 0;
150 else if (Mips::LO64RegClass.contains(SrcReg))
151 Opc = Mips::MFLO64, SrcReg = 0;
152 else if (Mips::FGR64RegClass.contains(SrcReg))
153 Opc = Mips::DMFC1;
155 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
156 if (Mips::HI64RegClass.contains(DestReg))
157 Opc = Mips::MTHI64, DestReg = 0;
158 else if (Mips::LO64RegClass.contains(DestReg))
159 Opc = Mips::MTLO64, DestReg = 0;
160 else if (Mips::FGR64RegClass.contains(DestReg))
161 Opc = Mips::DMTC1;
163 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
164 if (Mips::MSA128BRegClass.contains(SrcReg))
165 Opc = Mips::MOVE_V;
193 if (Mips::GPR32RegClass.hasSubClassEq(RC))
194 Opc = Mips::SW;
195 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
196 Opc = Mips::SD;
197 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
198 Opc = Mips::STORE_ACC64;
199 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
200 Opc = Mips::STORE_ACC64DSP;
201 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
202 Opc = Mips::STORE_ACC128;
203 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
204 Opc = Mips::STORE_CCOND_DSP;
205 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
206 Opc = Mips::SWC1;
207 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
208 Opc = Mips::SDC1;
209 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
210 Opc = Mips::SDC164;
212 Opc = Mips::ST_B;
214 Opc = Mips::ST_H;
216 Opc = Mips::ST_W;
218 Opc = Mips::ST_D;
234 if (Mips::GPR32RegClass.hasSubClassEq(RC))
235 Opc = Mips::LW;
236 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
237 Opc = Mips::LD;
238 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
239 Opc = Mips::LOAD_ACC64;
240 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
241 Opc = Mips::LOAD_ACC64DSP;
242 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
243 Opc = Mips::LOAD_ACC128;
244 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
245 Opc = Mips::LOAD_CCOND_DSP;
246 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
247 Opc = Mips::LWC1;
248 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
249 Opc = Mips::LDC1;
250 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
251 Opc = Mips::LDC164;
253 Opc = Mips::LD_B;
255 Opc = Mips::LD_H;
257 Opc = Mips::LD_W;
259 Opc = Mips::LD_D;
274 case Mips::RetRA:
277 case Mips::PseudoMFHI:
278 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
281 case Mips::PseudoMFLO:
282 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
285 case Mips::PseudoMFHI64:
286 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
288 case Mips::PseudoMFLO64:
289 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
291 case Mips::PseudoMTLOHI:
292 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
294 case Mips::PseudoMTLOHI64:
295 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
297 case Mips::PseudoMTLOHI_DSP:
298 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
300 case Mips::PseudoCVT_S_W:
301 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
303 case Mips::PseudoCVT_D32_W:
304 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
306 case Mips::PseudoCVT_S_L:
307 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
309 case Mips::PseudoCVT_D64_W:
310 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
312 case Mips::PseudoCVT_D64_L:
313 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
315 case Mips::BuildPairF64:
318 case Mips::BuildPairF64_64:
321 case Mips::ExtractElementF64:
324 case Mips::ExtractElementF64_64:
327 case Mips::MIPSeh_return32:
328 case Mips::MIPSeh_return64:
342 case Mips::BEQ: return Mips::BNE;
343 case Mips::BNE: return Mips::BEQ;
344 case Mips::BGTZ: return Mips::BLEZ;
345 case Mips::BGEZ: return Mips::BLTZ;
346 case Mips::BLTZ: return Mips::BGEZ;
347 case Mips::BLEZ: return Mips::BGTZ;
348 case Mips::BEQ64: return Mips::BNE64;
349 case Mips::BNE64: return Mips::BEQ64;
350 case Mips::BGTZ64: return Mips::BLEZ64;
351 case Mips::BGEZ64: return Mips::BLTZ64;
352 case Mips::BLTZ64: return Mips::BGEZ64;
353 case Mips::BLEZ64: return Mips::BGTZ64;
354 case Mips::BC1T: return Mips::BC1F;
355 case Mips::BC1F: return Mips::BC1T;
365 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
366 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
386 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
387 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
389 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
421 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
422 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
423 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
424 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
425 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
426 Opc == Mips::J) ?
435 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
436 .addReg(Mips::RA_64);
438 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA);
481 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
482 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
503 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
506 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
521 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
524 if (SubIdx == Mips::sub_hi && FP64) {
536 BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg).addReg(
539 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
547 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
566 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
584 BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
588 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
598 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
599 unsigned SP = STI.isGP64bit() ? Mips::SP_64 : Mips::SP;
600 unsigned RA = STI.isGP64bit() ? Mips::RA_64 : Mips::RA;
601 unsigned T9 = STI.isGP64bit() ? Mips::T9_64 : Mips::T9;
602 unsigned ZERO = STI.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
