Lines Matching refs:Or
272 // If this is a type than can be sign or zero-extended to a basic operation
437 // R0 or X0 to the result register, as the result may be used in a load,
438 // store, add-immediate, or isel that won't permit this. (Though
867 // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
872 // stack slot and 4-byte store/load sequence. Or just sext the 4-byte
987 // register, and return the register (or zero if we can't handle it).
1112 case ISD::OR:
1113 Opc = IsGPRC ? PPC::OR : PPC::OR8;
1141 case PPC::OR:
1544 // register. This avoids an unnecessary extend or truncate.
1787 case Instruction::Or:
1788 return SelectBinaryIntOp(I, ISD::OR);
1812 // the register number (or zero if we failed to handle it).
1863 // the register number (or zero if we failed to handle it).
1870 // addresses, constant pool entries, or jump tables. How we generate
1871 // code for these may depend on small, medium, or large code model.
1876 // what follows assumes everything's a generic (or TLS) global address.
1890 // or externally available linkage, a non-local function address, or a
1891 // jump table address (not yet needed), or if we are generating code
1920 // the register number (or zero if we failed to handle it).
1952 // the register number (or zero if we failed to handle it).
1973 // Handle the high-order 32 bits (if shifted) or the whole 32 bits
2009 // the register number (or zero if we failed to handle it).
2050 // number (or zero if we failed to handle it).
2069 // return the register number (or zero if we failed to handle it).
2105 // Combine load followed by zero- or sign-extend.
2174 // or vector args.
2214 // assigning R0 or X0 to the output register for GPRC and G8RC
