Lines Matching refs:AMDGPUTargetLowering
88 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
98 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
106 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
389 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
393 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
399 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
405 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
410 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
427 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
432 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
437 bool AMDGPUTargetLowering
442 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
448 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
456 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
464 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
468 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
482 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
488 SDValue AMDGPUTargetLowering::LowerReturn(
502 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
521 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
548 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
593 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
671 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
742 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
754 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
766 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
781 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
921 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
933 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
948 SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
1003 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
1039 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1097 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1123 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1222 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1224 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1279 SDValue AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {
1360 SDValue AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const {
1425 SDValue AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const {
1429 SDValue AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
1447 SDValue AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const {
1508 SDValue AMDGPUTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const {
1512 SDValue AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const {
1524 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1628 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1666 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1689 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1745 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1769 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1776 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1799 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1818 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1830 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1900 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
1931 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2038 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2070 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2080 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2090 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2107 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2180 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2246 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
