Lines Matching refs:Slot
438 llvm_unreachable("Wrong Swizzle for Trans Slot");
529 /// Instructions in Trans slot can't read gpr at cycle 0 if they also read
1236 return Ops[Slot]; \
1239 static unsigned getSlotedOps(unsigned Op, unsigned Slot) {
1266 MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
1276 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
1278 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
1299 getSlotedOps(AMDGPU::OpName::pred_sel, Slot)));
1305 getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
