Lines Matching defs:SP
57 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
96 Reg = SP::I0 + Offset/8;
99 Reg = SP::D0 + Offset/8;
102 Reg = SP::F1 + Offset/4;
105 Reg = SP::Q0 + Offset/16;
134 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
141 unsigned Reg = SP::I0 + Offset/8;
164 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
165 if (Reg >= SP::I0 && Reg <= SP::I7)
166 return Reg - SP::I0 + SP::O0;
225 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
227 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy()));
378 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
395 &SP::IntRegsRegClass);
404 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
488 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
498 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
516 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
637 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
776 // store SRet argument in %sp+64
777 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
794 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
827 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
837 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
868 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
1023 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1030 unsigned IReg = SP::I0 + Offset/8;
1082 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1129 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1131 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
1139 // Store to %sp+BIAS+128+Offset
1181 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
1183 // %sp+BIAS+128 in ours.
1373 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1374 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1375 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1376 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1378 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1576 setExceptionPointerRegister(SP::I0);
1577 setExceptionSelectorRegister(SP::I1);
1579 setStackPointerRegisterToSaveRestore(SP::O6);
1896 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
1906 Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
1917 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
1950 DAG.getRegister(SP::G7, PtrVT), Offset,
1963 DAG.getRegister(SP::G7, PtrVT), Offset);
2369 DAG.getRegister(SP::I6, TLI.getPointerTy()),
2406 unsigned SPReg = SP::O6;
2407 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2408 SP, Size); // Value
2409 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2437 unsigned FrameReg = SP::I6;
2494 unsigned RetReg = MF.addLiveIn(SP::I7,
2526 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2528 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2535 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2537 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2571 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2572 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2599 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2600 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2651 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2653 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2662 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2664 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2841 case SP::SELECT_CC_Int_ICC:
2842 case SP::SELECT_CC_FP_ICC:
2843 case SP::SELECT_CC_DFP_ICC:
2844 case SP::SELECT_CC_QFP_ICC:
2845 return expandSelectCC(MI, BB, SP::BCOND);
2846 case SP::SELECT_CC_Int_FCC:
2847 case SP::SELECT_CC_FP_FCC:
2848 case SP::SELECT_CC_DFP_FCC:
2849 case SP::SELECT_CC_QFP_FCC:
2850 return expandSelectCC(MI, BB, SP::FBCOND);
2852 case SP::ATOMIC_LOAD_ADD_32:
2853 return expandAtomicRMW(MI, BB, SP::ADDrr);
2854 case SP::ATOMIC_LOAD_ADD_64:
2855 return expandAtomicRMW(MI, BB, SP::ADDXrr);
2856 case SP::ATOMIC_LOAD_SUB_32:
2857 return expandAtomicRMW(MI, BB, SP::SUBrr);
2858 case SP::ATOMIC_LOAD_SUB_64:
2859 return expandAtomicRMW(MI, BB, SP::SUBXrr);
2860 case SP::ATOMIC_LOAD_AND_32:
2861 return expandAtomicRMW(MI, BB, SP::ANDrr);
2862 case SP::ATOMIC_LOAD_AND_64:
2863 return expandAtomicRMW(MI, BB, SP::ANDXrr);
2864 case SP::ATOMIC_LOAD_OR_32:
2865 return expandAtomicRMW(MI, BB, SP::ORrr);
2866 case SP::ATOMIC_LOAD_OR_64:
2867 return expandAtomicRMW(MI, BB, SP::ORXrr);
2868 case SP::ATOMIC_LOAD_XOR_32:
2869 return expandAtomicRMW(MI, BB, SP::XORrr);
2870 case SP::ATOMIC_LOAD_XOR_64:
2871 return expandAtomicRMW(MI, BB, SP::XORXrr);
2872 case SP::ATOMIC_LOAD_NAND_32:
2873 return expandAtomicRMW(MI, BB, SP::ANDrr);
2874 case SP::ATOMIC_LOAD_NAND_64:
2875 return expandAtomicRMW(MI, BB, SP::ANDXrr);
2877 case SP::ATOMIC_SWAP_64:
2880 case SP::ATOMIC_LOAD_MAX_32:
2881 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G);
2882 case SP::ATOMIC_LOAD_MAX_64:
2883 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G);
2884 case SP::ATOMIC_LOAD_MIN_32:
2885 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE);
2886 case SP::ATOMIC_LOAD_MIN_64:
2887 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE);
2888 case SP::ATOMIC_LOAD_UMAX_32:
2889 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU);
2890 case SP::ATOMIC_LOAD_UMAX_64:
2891 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU);
2892 case SP::ATOMIC_LOAD_UMIN_32:
2893 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU);
2894 case SP::ATOMIC_LOAD_UMIN_64:
2895 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU);
2951 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
2989 bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg));
2991 is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
2994 BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg)
3021 BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg)
3028 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg);
3036 if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 ||
3037 MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) {
3040 BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1);
3043 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg)
3046 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg);
3047 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND))
3138 return std::make_pair(0U, &SP::IntRegsRegClass);
