Lines Matching refs:X86
1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
10 // This file is part of the X86 Disassembler.
33 #define DEBUG_TYPE "x86-disassembler"
60 namespace X86 {
85 (X86::Mode16Bit | X86::Mode32Bit | X86::Mode64Bit)) {
86 case X86::Mode16Bit:
89 case X86::Mode32Bit:
92 case X86::Mode64Bit:
175 #define ENTRY(x) X86::x,
228 X86::CS,
229 X86::SS,
230 X86::DS,
231 X86::ES,
232 X86::FS,
233 X86::GS
244 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::RSI;
246 baseRegNo = insn.prefixPresent[0x67] ? X86::SI : X86::ESI;
249 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI;
269 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::RDI;
271 baseRegNo = insn.prefixPresent[0x67] ? X86::DI : X86::EDI;
274 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::DI;
320 // By default sign-extend all X86 immediates based on their encoding.
328 // Special case those X86 instructions that use the imm8 as a set of
330 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
331 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
332 Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
333 Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&
334 Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &&
335 Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri &&
336 Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri &&
337 Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri &&
338 Opcode != X86::VINSERTPSrr)
359 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
362 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
365 mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));
426 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
471 baseReg = MCOperand::CreateReg(X86::x); break;
486 bool IndexIs128 = (Opcode == X86::VGATHERDPDrm ||
487 Opcode == X86::VGATHERDPDYrm ||
488 Opcode == X86::VGATHERQPDrm ||
489 Opcode == X86::VGATHERDPSrm ||
490 Opcode == X86::VGATHERQPSrm ||
491 Opcode == X86::VPGATHERDQrm ||
492 Opcode == X86::VPGATHERDQYrm ||
493 Opcode == X86::VPGATHERQQrm ||
494 Opcode == X86::VPGATHERDDrm ||
495 Opcode == X86::VPGATHERQDrm);
496 bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm ||
497 Opcode == X86::VGATHERDPSYrm ||
498 Opcode == X86::VGATHERQPSYrm ||
499 Opcode == X86::VGATHERDPDZrm ||
500 Opcode == X86::VPGATHERDQZrm ||
501 Opcode == X86::VPGATHERQQYrm ||
502 Opcode == X86::VPGATHERDDYrm ||
503 Opcode == X86::VPGATHERQDYrm);
504 bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm ||
505 Opcode == X86::VGATHERDPSZrm ||
506 Opcode == X86::VGATHERQPSZrm ||
507 Opcode == X86::VPGATHERQQZrm ||
508 Opcode == X86::VPGATHERDDZrm ||
509 Opcode == X86::VPGATHERQDZrm);
526 indexReg = MCOperand::CreateReg(X86::x); break;
552 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
560 baseReg = MCOperand::CreateReg(X86::BX);
561 indexReg = MCOperand::CreateReg(X86::SI);
564 baseReg = MCOperand::CreateReg(X86::BX);
565 indexReg = MCOperand::CreateReg(X86::DI);
568 baseReg = MCOperand::CreateReg(X86::BP);
569 indexReg = MCOperand::CreateReg(X86::SI);
572 baseReg = MCOperand::CreateReg(X86::BP);
573 indexReg = MCOperand::CreateReg(X86::DI);
587 baseReg = MCOperand::CreateReg(X86::x); break;
681 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
697 mcInst.addOperand(MCOperand::CreateReg(X86::K0 + maskRegNum));
784 if(mcInst.getOpcode() == X86::REP_PREFIX)
785 mcInst.setOpcode(X86::XRELEASE_PREFIX);
786 else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
787 mcInst.setOpcode(X86::XACQUIRE_PREFIX);
