Lines Matching refs:X86
1 //===-- X86CodeEmitter.cpp - Convert X86 code to machine code -------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
15 #include "X86.h"
38 #define DEBUG_TYPE "x86-emitter"
63 return "X86 Machine Code Emitter";
122 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
150 if (Desc.getOpcode() == X86::MOVPC32r)
151 emitInstruction(*I, &II->get(X86::POP32r));
160 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
162 /// size, and 3) use of X86-64 extended registers.
222 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
263 X86::reloc_pcrel_word, MBB));
277 if (Reloc == X86::reloc_picrel_word)
279 else if (Reloc == X86::reloc_pcrel_word)
289 if (Reloc == X86::reloc_absolute_dword)
301 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
303 // X86 never needs stubs because instruction selection will always pick
311 if (Reloc == X86::reloc_absolute_dword)
325 if (Reloc == X86::reloc_picrel_word)
327 else if (Reloc == X86::reloc_pcrel_word)
332 if (Reloc == X86::reloc_absolute_dword)
345 if (Reloc == X86::reloc_picrel_word)
347 else if (Reloc == X86::reloc_pcrel_word)
352 if (Reloc == X86::reloc_absolute_dword)
426 (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
427 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
485 if (BaseReg == X86::RIP ||
486 (Is64BitMode && DispForReloc)) { // [disp32+RIP] in X86-64 mode
504 if (BaseReg != 0 && BaseReg != X86::RIP)
516 if (BaseReg == 0 || // [disp32] in X86-32 mode
517 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
546 assert(IndexReg.getReg() != X86::ESP &&
547 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
613 const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
614 const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
617 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
619 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
627 const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
628 const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
631 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
633 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
642 const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
643 const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
646 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
648 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
700 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
732 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
735 case X86::CS: MCE.emitByte(0x2E); break;
736 case X86::SS: MCE.emitByte(0x36); break;
737 case X86::DS: MCE.emitByte(0x3E); break;
738 case X86::ES: MCE.emitByte(0x26); break;
739 case X86::FS: MCE.emitByte(0x64); break;
740 case X86::GS: MCE.emitByte(0x65); break;
859 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg()))
861 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg()))
864 CurOp = X86::AddrNumOperands;
893 X86::AddrBaseReg).getReg()))
896 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
900 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands);
913 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
916 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
1011 case X86::ADD16rr_DB: Desc = UpdateOp(MI, II, X86::OR16rr); break;
1012 case X86::ADD32rr_DB: Desc = UpdateOp(MI, II, X86::OR32rr); break;
1013 case X86::ADD64rr_DB: Desc = UpdateOp(MI, II, X86::OR64rr); break;
1014 case X86::ADD16ri_DB: Desc = UpdateOp(MI, II, X86::OR16ri); break;
1015 case X86::ADD32ri_DB: Desc = UpdateOp(MI, II, X86::OR32ri); break;
1016 case X86::ADD64ri32_DB: Desc = UpdateOp(MI, II, X86::OR64ri32); break;
1017 case X86::ADD16ri8_DB: Desc = UpdateOp(MI, II, X86::OR16ri8); break;
1018 case X86::ADD32ri8_DB: Desc = UpdateOp(MI, II, X86::OR32ri8); break;
1019 case X86::ADD64ri8_DB: Desc = UpdateOp(MI, II, X86::OR64ri8); break;
1020 case X86::ACQUIRE_MOV8rm: Desc = UpdateOp(MI, II, X86::MOV8rm); break;
1021 case X86::ACQUIRE_MOV16rm: Desc = UpdateOp(MI, II, X86::MOV16rm); break;
1022 case X86::ACQUIRE_MOV32rm: Desc = UpdateOp(MI, II, X86::MOV32rm); break;
1023 case X86::ACQUIRE_MOV64rm: Desc = UpdateOp(MI, II, X86::MOV64rm); break;
1024 case X86::RELEASE_MOV8mr: Desc = UpdateOp(MI, II, X86::MOV8mr); break;
1025 case X86::RELEASE_MOV16mr: Desc = UpdateOp(MI, II, X86::MOV16mr); break;
1026 case X86::RELEASE_MOV32mr: Desc = UpdateOp(MI, II, X86::MOV32mr); break;
1027 case X86::RELEASE_MOV64mr: Desc = UpdateOp(MI, II, X86::MOV64mr); break;
1099 llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
1109 case X86::Int_MemBarrier:
1135 case X86::SEH_PushReg:
1136 case X86::SEH_SaveReg:
1137 case X86::SEH_SaveXMM:
1138 case X86::SEH_StackAlloc:
1139 case X86::SEH_SetFrame:
1140 case X86::SEH_PushFrame:
1141 case X86::SEH_EndPrologue:
1144 case X86::MOVPC32r: {
1177 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
1183 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
1189 emitJumpTableAddress(MO.getIndex(), X86::reloc_pcrel_word);
1194 if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
1218 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
1219 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
1220 if (Opcode == X86::MOV32ri64)
1221 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
1223 if (Opcode == X86::MOV64ri)
1224 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
1253 unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
1281 int AddrOperands = X86::AddrNumOperands;
1324 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
1325 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
1326 if (Opcode == X86::MOV64ri32)
1327 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
1348 intptr_t PCAdj = (CurOp + X86::AddrNumOperands != NumOps) ?
1349 (MI.getOperand(CurOp+X86::AddrNumOperands).isImm() ?
1356 CurOp += X86::AddrNumOperands;
1368 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
1369 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
1370 if (Opcode == X86::MOV64mi32)
1371 X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
