Lines Matching refs:X86
1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
16 #include "X86.h"
161 bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
207 static std::pair<X86::CondCode, bool>
209 X86::CondCode CC = X86::COND_INVALID;
214 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
216 case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
218 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
220 case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
222 case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
223 case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
224 case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
225 case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
227 case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
230 case CmpInst::ICMP_EQ: CC = X86::COND_E; break;
231 case CmpInst::ICMP_NE: CC = X86::COND_NE; break;
232 case CmpInst::ICMP_UGT: CC = X86::COND_A; break;
233 case CmpInst::ICMP_UGE: CC = X86::COND_AE; break;
234 case CmpInst::ICMP_ULT: CC = X86::COND_B; break;
235 case CmpInst::ICMP_ULE: CC = X86::COND_BE; break;
236 case CmpInst::ICMP_SGT: CC = X86::COND_G; break;
237 case CmpInst::ICMP_SGE: CC = X86::COND_GE; break;
238 case CmpInst::ICMP_SLT: CC = X86::COND_L; break;
239 case CmpInst::ICMP_SLE: CC = X86::COND_LE; break;
282 bool X86FastISel::foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
302 X86::CondCode TmpCC;
308 case Intrinsic::umul_with_overflow: TmpCC = X86::COND_O; break;
310 case Intrinsic::usub_with_overflow: TmpCC = X86::COND_B; break;
352 // We only handle legal types. For example, on x86-32 the instruction
353 // selector contains all of the 64-bit instructions from x86-64,
373 Opc = X86::MOV8rm;
374 RC = &X86::GR8RegClass;
377 Opc = X86::MOV16rm;
378 RC = &X86::GR16RegClass;
381 Opc = X86::MOV32rm;
382 RC = &X86::GR32RegClass;
385 // Must be in x86-64 mode.
386 Opc = X86::MOV64rm;
387 RC = &X86::GR64RegClass;
391 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
392 RC = &X86::FR32RegClass;
394 Opc = X86::LD_Fp32m;
395 RC = &X86::RFP32RegClass;
400 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
401 RC = &X86::FR64RegClass;
403 Opc = X86::LD_Fp64m;
404 RC = &X86::RFP64RegClass;
435 unsigned AndResult = createResultReg(&X86::GR8RegClass);
437 TII.get(X86::AND8ri), AndResult)
442 case MVT::i8: Opc = X86::MOV8mr; break;
443 case MVT::i16: Opc = X86::MOV16mr; break;
444 case MVT::i32: Opc = X86::MOV32mr; break;
445 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
448 X86::VMOVSSmr : X86::MOVSSmr) : X86::ST_Fp32m;
452 (Subtarget->hasAVX() ? X86::VMOVSDmr : X86::MOVSDmr) : X86::ST_Fp64m;
456 Opc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
458 Opc = Subtarget->hasAVX() ? X86::VMOVUPSmr : X86::MOVUPSmr;
462 Opc = Subtarget->hasAVX() ? X86::VMOVAPDmr : X86::MOVAPDmr;
464 Opc = Subtarget->hasAVX() ? X86::VMOVUPDmr : X86::MOVUPDmr;
471 Opc = Subtarget->hasAVX() ? X86::VMOVDQAmr : X86::MOVDQAmr;
473 Opc = Subtarget->hasAVX() ? X86::VMOVDQUmr : X86::MOVDQUmr;
500 case MVT::i8: Opc = X86::MOV8mi; break;
501 case MVT::i16: Opc = X86::MOV16mi; break;
502 case MVT::i32: Opc = X86::MOV32mi; break;
506 Opc = X86::MOV64mi32;
579 AM.Base.Reg = X86::RIP;
604 Opc = X86::MOV64rm;
605 RC = &X86::GR64RegClass;
608 StubAM.Base.Reg = X86::RIP;
610 Opc = X86::MOV32rm;
611 RC = &X86::GR32RegClass;
836 // method, which is not guarantee for X86.
902 AM.Base.Reg = X86::RIP;
1023 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
1037 assert(DstVT == MVT::i32 && "X86 should always ext to i32");
1064 // The x86-64 ABI for returning structs by value requires that we copy
1073 unsigned RetReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
1081 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Subtarget->is64Bit() ? X86::RETQ : X86::RETL));
1121 case MVT::i8: return X86::CMP8rr;
1122 case MVT::i16: return X86::CMP16rr;
1123 case MVT::i32: return X86::CMP32rr;
1124 case MVT::i64: return X86::CMP64rr;
1126 return X86ScalarSSEf32 ? (HasAVX ? X86::VUCOMISSrr : X86::UCOMISSrr) : 0;
1128 return X86ScalarSSEf64 ? (HasAVX ? X86::VUCOMISDrr : X86::UCOMISDrr) : 0;
1139 case MVT::i8: return X86::CMP8ri;
1140 case MVT::i16: return X86::CMP16ri;
1141 case MVT::i32: return X86::CMP32ri;
1146 return X86::CMP64ri32;
1197 ResultReg = createResultReg(&X86::GR32RegClass);
1198 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV32r0),
1201 X86::sub_8bit);
1207 ResultReg = createResultReg(&X86::GR8RegClass);
1208 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV8ri),
1233 { X86::SETEr, X86::SETNPr, X86::AND8rr },
1234 { X86::SETNEr, X86::SETPr, X86::OR8rr }
1243 ResultReg = createResultReg(&X86::GR8RegClass);
1248 unsigned FlagReg1 = createResultReg(&X86::GR8RegClass);
1249 unsigned FlagReg2 = createResultReg(&X86::GR8RegClass);
1260 X86::CondCode CC;
1263 assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
1264 unsigned Opc = X86::getSETFromCond(CC);
1303 case MVT::i8: MovInst = X86::MOVZX32rr8; break;
1304 case MVT::i16: MovInst = X86::MOVZX32rr16; break;
1305 case MVT::i32: MovInst = X86::MOV32rr; break;
1309 unsigned Result32 = createResultReg(&X86::GR32RegClass);
1313 ResultReg = createResultReg(&X86::GR64RegClass);
1316 .addImm(0).addReg(Result32).addImm(X86::sub_32bit);
1339 X86::CondCode CC;
1390 assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
1392 BranchOpc = X86::GetCondBranchFromCond(CC);
1403 // X86 requires a second branch to handle UNE (and OEQ, which is mapped
1406 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86
1432 case MVT::i8: TestOpc = X86::TEST8ri; break;
1433 case MVT::i16: TestOpc = X86::TEST16ri; break;
1434 case MVT::i32: TestOpc = X86::TEST32ri; break;
1435 case MVT::i64: TestOpc = X86::TEST64ri32; break;
1443 unsigned JmpOpc = X86::JNE_4;
1446 JmpOpc = X86::JE_4;
1467 unsigned BranchOpc = X86::GetCondBranchFromCond(CC);
1486 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
1488 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JNE_4))
1503 CReg = X86::CL;
1504 RC = &X86::GR8RegClass;
1506 case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1507 case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1508 case Instruction::Shl: OpReg = X86::SHL8rCL; break;
1512 CReg = X86::CX;
1513 RC = &X86::GR16RegClass;
1515 case Instruction::LShr: OpReg = X86::SHR16rCL; break;
1516 case Instruction::AShr: OpReg = X86::SAR16rCL; break;
1517 case Instruction::Shl: OpReg = X86::SHL16rCL; break;
1521 CReg = X86::ECX;
1522 RC = &X86::GR32RegClass;
1524 case Instruction::LShr: OpReg = X86::SHR32rCL; break;
1525 case Instruction::AShr: OpReg = X86::SAR32rCL; break;
1526 case Instruction::Shl: OpReg = X86::SHL32rCL; break;
1530 CReg = X86::RCX;
1531 RC = &X86::GR64RegClass;
1533 case Instruction::LShr: OpReg = X86::SHR64rCL; break;
1534 case Instruction::AShr: OpReg = X86::SAR64rCL; break;
1535 case Instruction::Shl: OpReg = X86::SHL64rCL; break;
1554 // The shift instruction uses X86::CL. If we defined a super-register
1555 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
1556 if (CReg != X86::CL)
1558 TII.get(TargetOpcode::KILL), X86::CL)
1574 // For the X86 DIV/IDIV instruction, in most cases the dividend
1599 { &X86::GR8RegClass, X86::AX, 0, {
1600 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AL, S }, // SDiv
1601 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S }, // SRem
1602 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AL, U }, // UDiv
1603 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U }, // URem
1606 { &X86::GR16RegClass, X86::AX, X86::DX, {
1607 { X86::IDIV16r, X86::CWD, Copy, X86::AX, S }, // SDiv
1608 { X86::IDIV16r, X86::CWD, Copy, X86::DX, S }, // SRem
1609 { X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U }, // UDiv
1610 { X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U }, // URem
1613 { &X86::GR32RegClass, X86::EAX, X86::EDX, {
1614 { X86::IDIV32r, X86::CDQ, Copy, X86::EAX, S }, // SDiv
1615 { X86::IDIV32r, X86::CDQ, Copy, X86::EDX, S }, // SRem
1616 { X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U }, // UDiv
1617 { X86::DIV32r, X86::MOV32r0, Copy, X86::EDX, U }, // URem
1620 { &X86::GR64RegClass, X86::RAX, X86::RDX, {
1621 { X86::IDIV64r, X86::CQO, Copy, X86::RAX, S }, // SDiv
1622 { X86::IDIV64r, X86::CQO, Copy, X86::RDX, S }, // SRem
1623 { X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U }, // UDiv
1624 { X86::DIV64r, X86::MOV32r0, Copy, X86::RDX, U }, // URem
1671 unsigned Zero32 = createResultReg(&X86::GR32RegClass);
1673 TII.get(X86::MOV32r0), Zero32);
1681 .addReg(Zero32, 0, X86::sub_16bit);
1689 .addImm(0).addReg(Zero32).addImm(X86::sub_32bit);
1707 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) {
1708 unsigned SourceSuperReg = createResultReg(&X86::GR16RegClass);
1709 unsigned ResultSuperReg = createResultReg(&X86::GR16RegClass);
1711 TII.get(Copy), SourceSuperReg).addReg(X86::AX);
1714 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SHR16ri),
1719 /*Kill=*/true, X86::sub_8bit);
1746 X86::CondCode CC = X86::COND_NE;
1757 { X86::SETNPr, X86::SETEr , X86::TEST8rr },
1758 { X86::SETPr, X86::SETNEr, X86::OR8rr }
1775 assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
1788 unsigned FlagReg1 = createResultReg(&X86::GR8RegClass);
1789 unsigned FlagReg2 = createResultReg(&X86::GR8RegClass);
1796 unsigned TmpReg = createResultReg(&X86::GR8RegClass);
1826 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
1842 unsigned Opc = X86::getCMovFromCond(CC, RC->getSize());
1890 { { X86::CMPSSrr, X86::FsANDPSrr, X86::FsANDNPSrr, X86::FsORPSrr },
1891 { X86::VCMPSSrr, X86::VFsANDPSrr, X86::VFsANDNPSrr, X86::VFsORPSrr } },
1892 { { X86::CMPSDrr, X86::FsANDPDrr, X86::FsANDNPDrr, X86::FsORPDrr },
1893 { X86::VCMPSDrr, X86::VFsANDPDrr, X86::VFsANDNPDrr, X86::VFsORPDrr } }
1941 case MVT::i8: Opc = X86::CMOV_GR8; break;
1942 case MVT::i16: Opc = X86::CMOV_GR16; break;
1943 case MVT::i32: Opc = X86::CMOV_GR32; break;
1944 case MVT::f32: Opc = X86::CMOV_FR32; break;
1945 case MVT::f64: Opc = X86::CMOV_FR64; break;
1949 X86::CondCode CC = X86::COND_NE;
1958 if (CC > X86::LAST_VALID_COND)
1975 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
2053 unsigned ResultReg = createResultReg(&X86::FR64RegClass);
2055 TII.get(X86::CVTSS2SDrr), ResultReg)
2072 unsigned ResultReg = createResultReg(&X86::FR32RegClass);
2074 TII.get(X86::CVTSD2SSrr), ResultReg)
2107 // If we're on x86-32; we can't extract an i8 from a general register.
2110 (const TargetRegisterClass*)&X86::GR16_ABCDRegClass :
2111 (const TargetRegisterClass*)&X86::GR32_ABCDRegClass;
2121 X86::sub_8bit);
2197 case MVT::i32: Opc = X86::MOV32rm; RC = &X86::GR32RegClass; break;
2198 case MVT::i64: Opc = X86::MOV64rm; RC = &X86::GR64RegClass; break;
2209 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
2210 (FrameReg == X86::EBP && VT == MVT::i32)) &&
2310 X86::TRAP));
2327 {X86::SQRTSSr, X86::VSQRTSSr},
2328 {X86::SQRTSDr, X86::VSQRTSDr}
2335 case MVT::f32: Opc = SqrtOpc[0][HasAVX]; RC = &X86::FR32RegClass; break;
2336 case MVT::f64: Opc = SqrtOpc[1][HasAVX]; RC = &X86::FR64RegClass; break;
2397 BaseOpc = ISD::ADD; CondOpc = X86::SETOr; break;
2399 BaseOpc = ISD::ADD; CondOpc = X86::SETBr; break;
2401 BaseOpc = ISD::SUB; CondOpc = X86::SETOr; break;
2403 BaseOpc = ISD::SUB; CondOpc = X86::SETBr; break;
2405 BaseOpc = X86ISD::SMUL; CondOpc = X86::SETOr; break;
2407 BaseOpc = X86ISD::UMUL; CondOpc = X86::SETOr; break;
2433 // FastISel doesn't have a pattern for all X86::MUL*r and X86::IMUL*r. Emit
2437 { X86::MUL8r, X86::MUL16r, X86::MUL32r, X86::MUL64r };
2438 static const unsigned Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX };
2440 // the X86::MUL*r instruction.
2448 { X86::IMUL8r, X86::IMUL16rr, X86::IMUL32rr, X86::IMUL64rr };
2451 // X86::IMUL8r instruction.
2453 TII.get(TargetOpcode::COPY), X86::AL)
2501 { { X86::CVTTSS2SIrr, X86::VCVTTSS2SIrr },
2502 { X86::CVTTSS2SI64rr, X86::VCVTTSS2SI64rr } },
2503 { { X86::CVTTSD2SIrr, X86::VCVTTSD2SIrr },
2504 { X86::CVTTSD2SI64rr, X86::VCVTTSD2SI64rr } }
2602 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
2605 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9
2608 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2609 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2697 // x86-32. Special handling for x86-64 is implemented.
2706 if (X86::isCalleePop(CC, Subtarget->is64Bit(), isVarArg,
2778 // calling conventions on x86.
2947 TII.get(TargetOpcode::COPY), X86::EBX).addReg(Base);
2953 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2954 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2957 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV8ri),
2958 X86::AL).addImm(NumXMMRegs);
2967 CallOpc = X86::CALL64r;
2969 CallOpc = X86::CALL32r;
2978 CallOpc = X86::CALL64pcrel32;
2980 CallOpc = X86::CALLpcrel32;
2985 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3017 MIB.addReg(X86::EBX, RegState::Implicit);
3020 MIB.addReg(X86::AL, RegState::Implicit);
3069 if ((RVLocs[i].getLocReg() == X86::ST0 ||
3070 RVLocs[i].getLocReg() == X86::ST1)) {
3073 CopyReg = createResultReg(&X86::RFP80RegClass);
3076 TII.get(X86::FpPOP_RETVAL), CopyReg);
3089 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
3095 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
3180 Opc = X86::MOV8rm;
3181 RC = &X86::GR8RegClass;
3184 Opc = X86::MOV16rm;
3185 RC = &X86::GR16RegClass;
3188 Opc = X86::MOV32rm;
3189 RC = &X86::GR32RegClass;
3192 // Must be in x86-64 mode.
3193 Opc = X86::MOV64rm;
3194 RC = &X86::GR64RegClass;
3198 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
3199 RC = &X86::FR32RegClass;
3201 Opc = X86::LD_Fp32m;
3202 RC = &X86::RFP32RegClass;
3207 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
3208 RC = &X86::FR64RegClass;
3210 Opc = X86::LD_Fp64m;
3211 RC = &X86::RFP64RegClass;
3234 Opc = X86::MOV64ri;
3238 Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r;
3254 // x86-32 PIC requires a PIC base register for constant pools.
3265 PICBase = X86::RIP;
3293 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
3313 Opc = X86::FsFLD0SS;
3314 RC = &X86::FR32RegClass;
3316 Opc = X86::LD_Fp032;
3317 RC = &X86::RFP32RegClass;
3322 Opc = X86::FsFLD0SD;
3323 RC = &X86::FR64RegClass;
3325 Opc = X86::LD_Fp064;
3326 RC = &X86::RFP64RegClass;
3371 FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo,
