Lines Matching refs:X86
1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
15 #include "X86.h"
38 #define DEBUG_TYPE "x86-isel"
94 return RegNode->getReg() == X86::RIP;
143 /// ISel - X86 specific code to select X86 machine instructions for
162 return "X86 DAG->DAG Instruction Selection";
498 // late" legalization of these inline with the X86 isel pass.
571 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
599 if (!X86::isOffsetSuitableForCodeModel(Val, M,
620 // gs:0 (or fs:0 on X86-64) contains its own address.
627 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
630 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
650 // Handle X86-64 rip-relative addresses. We check this before checking direct
653 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
695 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
700 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
760 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
1327 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1329 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1438 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1452 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1503 // For X86-64, we should always use lea to materialize RIP relative
1537 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1618 X86::LOCK_ADD8mi,
1619 X86::LOCK_ADD8mr,
1620 X86::LOCK_ADD16mi8,
1621 X86::LOCK_ADD16mi,
1622 X86::LOCK_ADD16mr,
1623 X86::LOCK_ADD32mi8,
1624 X86::LOCK_ADD32mi,
1625 X86::LOCK_ADD32mr,
1626 X86::LOCK_ADD64mi8,
1627 X86::LOCK_ADD64mi32,
1628 X86::LOCK_ADD64mr,
1631 X86::LOCK_SUB8mi,
1632 X86::LOCK_SUB8mr,
1633 X86::LOCK_SUB16mi8,
1634 X86::LOCK_SUB16mi,
1635 X86::LOCK_SUB16mr,
1636 X86::LOCK_SUB32mi8,
1637 X86::LOCK_SUB32mi,
1638 X86::LOCK_SUB32mr,
1639 X86::LOCK_SUB64mi8,
1640 X86::LOCK_SUB64mi32,
1641 X86::LOCK_SUB64mr,
1645 X86::LOCK_INC8m,
1648 X86::LOCK_INC16m,
1651 X86::LOCK_INC32m,
1654 X86::LOCK_INC64m,
1658 X86::LOCK_DEC8m,
1661 X86::LOCK_DEC16m,
1664 X86::LOCK_DEC32m,
1667 X86::LOCK_DEC64m,
1670 X86::LOCK_OR8mi,
1671 X86::LOCK_OR8mr,
1672 X86::LOCK_OR16mi8,
1673 X86::LOCK_OR16mi,
1674 X86::LOCK_OR16mr,
1675 X86::LOCK_OR32mi8,
1676 X86::LOCK_OR32mi,
1677 X86::LOCK_OR32mr,
1678 X86::LOCK_OR64mi8,
1679 X86::LOCK_OR64mi32,
1680 X86::LOCK_OR64mr,
1683 X86::LOCK_AND8mi,
1684 X86::LOCK_AND8mr,
1685 X86::LOCK_AND16mi8,
1686 X86::LOCK_AND16mi,
1687 X86::LOCK_AND16mr,
1688 X86::LOCK_AND32mi8,
1689 X86::LOCK_AND32mi,
1690 X86::LOCK_AND32mr,
1691 X86::LOCK_AND64mi8,
1692 X86::LOCK_AND64mi32,
1693 X86::LOCK_AND64mr,
1696 X86::LOCK_XOR8mi,
1697 X86::LOCK_XOR8mr,
1698 X86::LOCK_XOR16mi8,
1699 X86::LOCK_XOR16mi,
1700 X86::LOCK_XOR16mr,
1701 X86::LOCK_XOR32mi8,
1702 X86::LOCK_XOR32mi,
1703 X86::LOCK_XOR32mr,
1704 X86::LOCK_XOR64mi8,
1705 X86::LOCK_XOR64mi32,
1706 X86::LOCK_XOR64mr,
1745 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1754 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1757 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1872 X86::EFLAGS)
1884 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1885 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1886 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1887 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1888 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
1889 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
1890 case X86::CMOVA16rr: case X86::CMOVA16rm:
1891 case X86::CMOVA32rr: case X86::CMOVA32rm:
1892 case X86::CMOVA64rr: case X86::CMOVA64rm:
1893 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1894 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1895 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1896 case X86::CMOVB16rr: case X86::CMOVB16rm:
1897 case X86::CMOVB32rr: case X86::CMOVB32rm:
1898 case X86::CMOVB64rr: case X86::CMOVB64rm:
1899 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1900 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1901 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1902 case X86::CMOVE16rr: case X86::CMOVE16rm:
1903 case X86::CMOVE32rr: case X86::CMOVE32rm:
1904 case X86::CMOVE64rr: case X86::CMOVE64rm:
1905 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1906 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1907 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1908 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1909 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1910 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1911 case X86::CMOVP16rr: case X86::CMOVP16rm:
1912 case X86::CMOVP32rr: case X86::CMOVP32rm:
1913 case X86::CMOVP64rr: case X86::CMOVP64rm:
2009 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
2013 if (LdVT == MVT::i64) return X86::DEC64m;
2014 if (LdVT == MVT::i32) return X86::DEC32m;
2015 if (LdVT == MVT::i16) return X86::DEC16m;
2016 if (LdVT == MVT::i8) return X86::DEC8m;
2019 if (LdVT == MVT::i64) return X86::INC64m;
2020 if (LdVT == MVT::i32) return X86::INC32m;
2021 if (LdVT == MVT::i16) return X86::INC16m;
2022 if (LdVT == MVT::i8) return X86::INC8m;
2099 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2100 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2101 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2102 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2103 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2104 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2105 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2106 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2107 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2108 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2109 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2110 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2111 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2112 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2113 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2114 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2187 ShlOp = X86::SHL32ri;
2191 case ISD::AND: Op = X86::AND32ri8; break;
2192 case ISD::OR: Op = X86::OR32ri8; break;
2193 case ISD::XOR: Op = X86::XOR32ri8; break;
2198 ShlOp = X86::SHL64ri;
2202 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2203 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2204 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2222 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2223 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2224 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2225 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2251 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2252 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2253 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2254 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2255 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2256 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2261 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2262 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2263 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2264 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2271 case X86::IMUL8r:
2272 case X86::MUL8r:
2273 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2275 case X86::IMUL16r:
2276 case X86::MUL16r:
2277 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2279 case X86::IMUL32r:
2280 case X86::MUL32r:
2281 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2283 case X86::IMUL64r:
2284 case X86::MUL64r:
2285 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2287 case X86::MULX32rr:
2288 SrcReg = X86::EDX; LoReg = HiReg = 0;
2290 case X86::MULX64rr:
2291 SrcReg = X86::RDX; LoReg = HiReg = 0;
2312 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2330 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2344 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2347 X86::AX, MVT::i16, InFlag);
2353 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2356 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2361 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2398 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2399 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2400 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2401 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2406 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2407 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2408 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2409 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2418 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2419 SExtOpcode = X86::CBW;
2422 LoReg = X86::AX; HiReg = X86::DX;
2423 ClrReg = X86::DX;
2424 SExtOpcode = X86::CWD;
2427 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2428 SExtOpcode = X86::CDQ;
2431 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2432 SExtOpcode = X86::CQO;
2448 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2454 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2457 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2469 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
2475 CurDAG->getTargetConstant(X86::sub_16bit, MVT::i32)),
2485 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
2517 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2520 X86::AX, MVT::i16, InFlag);
2528 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2531 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2536 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2576 X86::isZeroNode(N1)) {
2587 // On x86-32, only the ABCD registers have 8-bit subregisters.
2591 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2592 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2596 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2601 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2605 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2626 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2627 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2628 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2632 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2636 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2642 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2660 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2664 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2682 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2686 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2783 /// X86-specific DAG, ready for instruction scheduling.
