Lines Matching refs:CMOV
543 // X86 wants to expand cmov itself.
1599 // Predictable cmov don't hurt on atom because it's in-order.
3624 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3625 /// code. Current x86 isa includes the following FP cmov instructions:
10658 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10659 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10661 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10662 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12702 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
12703 // widen the cmov and push the truncate through. This avoids introducing a new
12712 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
12713 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
12717 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
12721 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14500 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
14928 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
14980 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16508 case X86ISD::CMOV: return "X86ISD::CMOV";
19789 // where Op could be BRCOND or CMOV.
19864 case X86ISD::CMOV: {
19908 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
19914 // If the flag operand isn't dead, don't touch this CMOV.
19942 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
20043 // of CMOV and CMP.
20072 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
20774 // Generate NEG and CMOV for integer abs.
20778 // Since X86 does not have CMOV for 8-bit integer, we don't convert
20779 // 8-bit integer abs to NEG and CMOV.
20788 // and change it to SUB and CMOV.
20796 // Generate SUB & CMOV.
20803 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
21976 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
