Lines Matching refs:X86
1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
15 #include "X86.h"
42 #define DEBUG_TYPE "x86-instr-info"
53 " fuse, but the X86 backend currently can't"),
103 (STI.is64Bit() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
104 (STI.is64Bit() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
108 { X86::ADC32ri, X86::ADC32mi, 0 },
109 { X86::ADC32ri8, X86::ADC32mi8, 0 },
110 { X86::ADC32rr, X86::ADC32mr, 0 },
111 { X86::ADC64ri32, X86::ADC64mi32, 0 },
112 { X86::ADC64ri8, X86::ADC64mi8, 0 },
113 { X86::ADC64rr, X86::ADC64mr, 0 },
114 { X86::ADD16ri, X86::ADD16mi, 0 },
115 { X86::ADD16ri8, X86::ADD16mi8, 0 },
116 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
117 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
118 { X86::ADD16rr, X86::ADD16mr, 0 },
119 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
120 { X86::ADD32ri, X86::ADD32mi, 0 },
121 { X86::ADD32ri8, X86::ADD32mi8, 0 },
122 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
123 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
124 { X86::ADD32rr, X86::ADD32mr, 0 },
125 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
126 { X86::ADD64ri32, X86::ADD64mi32, 0 },
127 { X86::ADD64ri8, X86::ADD64mi8, 0 },
128 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
129 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
130 { X86::ADD64rr, X86::ADD64mr, 0 },
131 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
132 { X86::ADD8ri, X86::ADD8mi, 0 },
133 { X86::ADD8rr, X86::ADD8mr, 0 },
134 { X86::AND16ri, X86::AND16mi, 0 },
135 { X86::AND16ri8, X86::AND16mi8, 0 },
136 { X86::AND16rr, X86::AND16mr, 0 },
137 { X86::AND32ri, X86::AND32mi, 0 },
138 { X86::AND32ri8, X86::AND32mi8, 0 },
139 { X86::AND32rr, X86::AND32mr, 0 },
140 { X86::AND64ri32, X86::AND64mi32, 0 },
141 { X86::AND64ri8, X86::AND64mi8, 0 },
142 { X86::AND64rr, X86::AND64mr, 0 },
143 { X86::AND8ri, X86::AND8mi, 0 },
144 { X86::AND8rr, X86::AND8mr, 0 },
145 { X86::DEC16r, X86::DEC16m, 0 },
146 { X86::DEC32r, X86::DEC32m, 0 },
147 { X86::DEC64_16r, X86::DEC64_16m, 0 },
148 { X86::DEC64_32r, X86::DEC64_32m, 0 },
149 { X86::DEC64r, X86::DEC64m, 0 },
150 { X86::DEC8r, X86::DEC8m, 0 },
151 { X86::INC16r, X86::INC16m, 0 },
152 { X86::INC32r, X86::INC32m, 0 },
153 { X86::INC64_16r, X86::INC64_16m, 0 },
154 { X86::INC64_32r, X86::INC64_32m, 0 },
155 { X86::INC64r, X86::INC64m, 0 },
156 { X86::INC8r, X86::INC8m, 0 },
157 { X86::NEG16r, X86::NEG16m, 0 },
158 { X86::NEG32r, X86::NEG32m, 0 },
159 { X86::NEG64r, X86::NEG64m, 0 },
160 { X86::NEG8r, X86::NEG8m, 0 },
161 { X86::NOT16r, X86::NOT16m, 0 },
162 { X86::NOT32r, X86::NOT32m, 0 },
163 { X86::NOT64r, X86::NOT64m, 0 },
164 { X86::NOT8r, X86::NOT8m, 0 },
165 { X86::OR16ri, X86::OR16mi, 0 },
166 { X86::OR16ri8, X86::OR16mi8, 0 },
167 { X86::OR16rr, X86::OR16mr, 0 },
168 { X86::OR32ri, X86::OR32mi, 0 },
169 { X86::OR32ri8, X86::OR32mi8, 0 },
170 { X86::OR32rr, X86::OR32mr, 0 },
171 { X86::OR64ri32, X86::OR64mi32, 0 },
172 { X86::OR64ri8, X86::OR64mi8, 0 },
173 { X86::OR64rr, X86::OR64mr, 0 },
174 { X86::OR8ri, X86::OR8mi, 0 },
175 { X86::OR8rr, X86::OR8mr, 0 },
176 { X86::ROL16r1, X86::ROL16m1, 0 },
177 { X86::ROL16rCL, X86::ROL16mCL, 0 },
178 { X86::ROL16ri, X86::ROL16mi, 0 },
179 { X86::ROL32r1, X86::ROL32m1, 0 },
180 { X86::ROL32rCL, X86::ROL32mCL, 0 },
181 { X86::ROL32ri, X86::ROL32mi, 0 },
182 { X86::ROL64r1, X86::ROL64m1, 0 },
183 { X86::ROL64rCL, X86::ROL64mCL, 0 },
184 { X86::ROL64ri, X86::ROL64mi, 0 },
185 { X86::ROL8r1, X86::ROL8m1, 0 },
186 { X86::ROL8rCL, X86::ROL8mCL, 0 },
187 { X86::ROL8ri, X86::ROL8mi, 0 },
188 { X86::ROR16r1, X86::ROR16m1, 0 },
189 { X86::ROR16rCL, X86::ROR16mCL, 0 },
190 { X86::ROR16ri, X86::ROR16mi, 0 },
191 { X86::ROR32r1, X86::ROR32m1, 0 },
192 { X86::ROR32rCL, X86::ROR32mCL, 0 },
193 { X86::ROR32ri, X86::ROR32mi, 0 },
194 { X86::ROR64r1, X86::ROR64m1, 0 },
195 { X86::ROR64rCL, X86::ROR64mCL, 0 },
196 { X86::ROR64ri, X86::ROR64mi, 0 },
197 { X86::ROR8r1, X86::ROR8m1, 0 },
198 { X86::ROR8rCL, X86::ROR8mCL, 0 },
199 { X86::ROR8ri, X86::ROR8mi, 0 },
200 { X86::SAR16r1, X86::SAR16m1, 0 },
201 { X86::SAR16rCL, X86::SAR16mCL, 0 },
202 { X86::SAR16ri, X86::SAR16mi, 0 },
203 { X86::SAR32r1, X86::SAR32m1, 0 },
204 { X86::SAR32rCL, X86::SAR32mCL, 0 },
205 { X86::SAR32ri, X86::SAR32mi, 0 },
206 { X86::SAR64r1, X86::SAR64m1, 0 },
207 { X86::SAR64rCL, X86::SAR64mCL, 0 },
208 { X86::SAR64ri, X86::SAR64mi, 0 },
209 { X86::SAR8r1, X86::SAR8m1, 0 },
210 { X86::SAR8rCL, X86::SAR8mCL, 0 },
211 { X86::SAR8ri, X86::SAR8mi, 0 },
212 { X86::SBB32ri, X86::SBB32mi, 0 },
213 { X86::SBB32ri8, X86::SBB32mi8, 0 },
214 { X86::SBB32rr, X86::SBB32mr, 0 },
215 { X86::SBB64ri32, X86::SBB64mi32, 0 },
216 { X86::SBB64ri8, X86::SBB64mi8, 0 },
217 { X86::SBB64rr, X86::SBB64mr, 0 },
218 { X86::SHL16rCL, X86::SHL16mCL, 0 },
219 { X86::SHL16ri, X86::SHL16mi, 0 },
220 { X86::SHL32rCL, X86::SHL32mCL, 0 },
221 { X86::SHL32ri, X86::SHL32mi, 0 },
222 { X86::SHL64rCL, X86::SHL64mCL, 0 },
223 { X86::SHL64ri, X86::SHL64mi, 0 },
224 { X86::SHL8rCL, X86::SHL8mCL, 0 },
225 { X86::SHL8ri, X86::SHL8mi, 0 },
226 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
227 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
228 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
229 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
230 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
231 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
232 { X86::SHR16r1, X86::SHR16m1, 0 },
233 { X86::SHR16rCL, X86::SHR16mCL, 0 },
234 { X86::SHR16ri, X86::SHR16mi, 0 },
235 { X86::SHR32r1, X86::SHR32m1, 0 },
236 { X86::SHR32rCL, X86::SHR32mCL, 0 },
237 { X86::SHR32ri, X86::SHR32mi, 0 },
238 { X86::SHR64r1, X86::SHR64m1, 0 },
239 { X86::SHR64rCL, X86::SHR64mCL, 0 },
240 { X86::SHR64ri, X86::SHR64mi, 0 },
241 { X86::SHR8r1, X86::SHR8m1, 0 },
242 { X86::SHR8rCL, X86::SHR8mCL, 0 },
243 { X86::SHR8ri, X86::SHR8mi, 0 },
244 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
245 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
246 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
247 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
248 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
249 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
250 { X86::SUB16ri, X86::SUB16mi, 0 },
251 { X86::SUB16ri8, X86::SUB16mi8, 0 },
252 { X86::SUB16rr, X86::SUB16mr, 0 },
253 { X86::SUB32ri, X86::SUB32mi, 0 },
254 { X86::SUB32ri8, X86::SUB32mi8, 0 },
255 { X86::SUB32rr, X86::SUB32mr, 0 },
256 { X86::SUB64ri32, X86::SUB64mi32, 0 },
257 { X86::SUB64ri8, X86::SUB64mi8, 0 },
258 { X86::SUB64rr, X86::SUB64mr, 0 },
259 { X86::SUB8ri, X86::SUB8mi, 0 },
260 { X86::SUB8rr, X86::SUB8mr, 0 },
261 { X86::XOR16ri, X86::XOR16mi, 0 },
262 { X86::XOR16ri8, X86::XOR16mi8, 0 },
263 { X86::XOR16rr, X86::XOR16mr, 0 },
264 { X86::XOR32ri, X86::XOR32mi, 0 },
265 { X86::XOR32ri8, X86::XOR32mi8, 0 },
266 { X86::XOR32rr, X86::XOR32mr, 0 },
267 { X86::XOR64ri32, X86::XOR64mi32, 0 },
268 { X86::XOR64ri8, X86::XOR64mi8, 0 },
269 { X86::XOR64rr, X86::XOR64mr, 0 },
270 { X86::XOR8ri, X86::XOR8mi, 0 },
271 { X86::XOR8rr, X86::XOR8mr, 0 }
285 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
286 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
287 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
288 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
289 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
290 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
291 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
292 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
293 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
294 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
295 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
296 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
297 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
298 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
299 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
300 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
301 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
302 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
303 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
304 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
305 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
306 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
307 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
308 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
309 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
310 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
311 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
312 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
313 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
314 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
315 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
316 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
317 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
318 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
319 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
320 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
321 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
322 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
323 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
324 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
325 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
326 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
327 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
328 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
329 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
330 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
331 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
332 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
333 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
334 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
335 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
336 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
337 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
338 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
339 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
340 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
341 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
342 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
343 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
344 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
345 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
346 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
347 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
348 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
349 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
350 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
351 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
352 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
353 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
354 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
355 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
356 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
357 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
358 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
359 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
361 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
362 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
363 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
364 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
365 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
366 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
367 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
368 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
369 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
370 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
371 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
373 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
374 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
375 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
376 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
377 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
378 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
380 { X86::VMOVPDI2DIZrr,X86::VMOVPDI2DIZmr, TB_FOLDED_STORE }
392 { X86::CMP16rr, X86::CMP16rm, 0 },
393 { X86::CMP32rr, X86::CMP32rm, 0 },
394 { X86::CMP64rr, X86::CMP64rm, 0 },
395 { X86::CMP8rr, X86::CMP8rm, 0 },
396 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
397 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
398 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
399 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
400 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
401 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
402 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
403 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
404 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
405 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
406 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
407 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
408 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
409 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
410 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
411 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
412 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
413 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
414 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
415 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
416 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
417 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
418 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
419 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
420 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
421 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
422 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
423 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
424 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
425 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
426 { X86::MOV16rr, X86::MOV16rm, 0 },
427 { X86::MOV32rr, X86::MOV32rm, 0 },
428 { X86::MOV64rr, X86::MOV64rm, 0 },
429 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
430 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
431 { X86::MOV8rr, X86::MOV8rm, 0 },
432 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
433 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
434 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
435 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
436 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
437 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
438 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
439 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
440 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
441 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
442 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
443 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
444 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
445 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
446 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
447 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
448 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
449 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
450 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
451 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
452 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
453 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
454 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
455 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
456 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
457 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
458 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
459 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
460 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
461 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
462 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
463 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
464 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
465 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
466 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
467 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
468 { X86::SQRTSDr, X86::SQRTSDm, 0 },
469 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
470 { X86::SQRTSSr, X86::SQRTSSm, 0 },
471 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
472 { X86::TEST16rr, X86::TEST16rm, 0 },
473 { X86::TEST32rr, X86::TEST32rm, 0 },
474 { X86::TEST64rr, X86::TEST64rm, 0 },
475 { X86::TEST8rr, X86::TEST8rm, 0 },
477 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
478 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
480 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
481 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
482 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
483 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
484 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
485 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
486 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
487 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
488 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
489 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
490 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
491 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
492 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
493 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
494 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
495 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
496 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
497 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
498 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
499 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
500 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
501 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
502 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
503 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
504 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
505 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
506 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
507 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
508 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
509 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
510 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
511 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
512 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
513 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
514 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
515 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
516 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
517 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
518 { X86::VRCPPSr, X86::VRCPPSm, 0 },
519 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, 0 },
520 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
521 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 },
522 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
523 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
524 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
525 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
526 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
529 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
530 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
531 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
532 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
533 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
534 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
535 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
538 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
539 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
540 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
541 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
542 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
543 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
544 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
545 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 },
546 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
547 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
548 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
549 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
550 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
553 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
554 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
555 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
556 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
557 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
558 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
559 { X86::BLCI32rr, X86::BLCI32rm, 0 },
560 { X86::BLCI64rr, X86::BLCI64rm, 0 },
561 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
562 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
563 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
564 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
565 { X86::BLCS32rr, X86::BLCS32rm, 0 },
566 { X86::BLCS64rr, X86::BLCS64rm, 0 },
567 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
568 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
569 { X86::BLSI32rr, X86::BLSI32rm, 0 },
570 { X86::BLSI64rr, X86::BLSI64rm, 0 },
571 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
572 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
573 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
574 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
575 { X86::BLSR32rr, X86::BLSR32rm, 0 },
576 { X86::BLSR64rr, X86::BLSR64rm, 0 },
577 { X86::BZHI32rr, X86::BZHI32rm, 0 },
578 { X86::BZHI64rr, X86::BZHI64rm, 0 },
579 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
580 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
581 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
582 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
583 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
584 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
585 { X86::RORX32ri, X86::RORX32mi, 0 },
586 { X86::RORX64ri, X86::RORX64mi, 0 },
587 { X86::SARX32rr, X86::SARX32rm, 0 },
588 { X86::SARX64rr, X86::SARX64rm, 0 },
589 { X86::SHRX32rr, X86::SHRX32rm, 0 },
590 { X86::SHRX64rr, X86::SHRX64rm, 0 },
591 { X86::SHLX32rr, X86::SHLX32rm, 0 },
592 { X86::SHLX64rr, X86::SHLX64rm, 0 },
593 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
594 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
595 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
596 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
597 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
598 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
599 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
602 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
603 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
604 { X86::VMOVDQA32rr, X86::VMOVDQA32rm, TB_ALIGN_64 },
605 { X86::VMOVDQA64rr, X86::VMOVDQA64rm, TB_ALIGN_64 },
606 { X86::VMOVDQU32rr, X86::VMOVDQU32rm, 0 },
607 { X86::VMOVDQU64rr, X86::VMOVDQU64rm, 0 },
608 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
609 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
612 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
613 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
614 { X86::VAESIMCrr, X86::VAESIMCrm, TB_ALIGN_16 },
615 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 },
629 { X86::ADC32rr, X86::ADC32rm, 0 },
630 { X86::ADC64rr, X86::ADC64rm, 0 },
631 { X86::ADD16rr, X86::ADD16rm, 0 },
632 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
633 { X86::ADD32rr, X86::ADD32rm, 0 },
634 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
635 { X86::ADD64rr, X86::ADD64rm, 0 },
636 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
637 { X86::ADD8rr, X86::ADD8rm, 0 },
638 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
639 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
640 { X86::ADDSDrr, X86::ADDSDrm, 0 },
641 { X86::ADDSSrr, X86::ADDSSrm, 0 },
642 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
643 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
644 { X86::AND16rr, X86::AND16rm, 0 },
645 { X86::AND32rr, X86::AND32rm, 0 },
646 { X86::AND64rr, X86
647 { X86::AND8rr, X86::AND8rm, 0 },
648 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
649 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
650 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
651 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
652 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
653 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
654 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
655 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
656 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
657 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
658 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
659 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
660 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
661 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
662 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
663 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
664 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
665 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
666 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
667 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
668 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
669 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
670 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
671 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
672 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
673 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
674 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
675 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
676 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
677 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
678 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
679 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
680 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
681 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
682 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
683 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
684 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
685 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
686 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
687 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
688 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
689 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
690 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
691 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
692 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
693 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
694 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
695 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
696 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
697 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
698 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
699 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
700 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
701 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
702 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
703 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
704 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
705 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
706 { X86::CMPSDrr, X86::CMPSDrm, 0 },
707 { X86::CMPSSrr, X86::CMPSSrm, 0 },
708 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
709 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
710 { X86::DIVSDrr, X86::DIVSDrm, 0 },
711 { X86::DIVSSrr, X86::DIVSSrm, 0 },
712 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
713 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
714 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
715 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
716 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
717 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
718 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
719 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
720 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
721 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
722 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
723 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
724 { X86::IMUL16rr, X86::IMUL16rm, 0 },
725 { X86::IMUL32rr, X86::IMUL32rm, 0 },
726 { X86::IMUL64rr, X86::IMUL64rm, 0 },
727 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
728 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
729 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
730 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
731 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
732 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
733 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
734 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
735 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
736 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
737 { X86::MAXSDrr, X86::MAXSDrm, 0 },
738 { X86::MAXSSrr, X86::MAXSSrm, 0 },
739 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
740 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
741 { X86::MINSDrr, X86::MINSDrm, 0 },
742 { X86::MINSSrr, X86::MINSSrm, 0 },
743 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
744 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
745 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
746 { X86::MULSDrr, X86::MULSDrm, 0 },
747 { X86::MULSSrr, X86::MULSSrm, 0 },
748 { X86::OR16rr, X86::OR16rm, 0 },
749 { X86::OR32rr, X86::OR32rm, 0 },
750 { X86::OR64rr, X86::OR64rm, 0 },
751 { X86::OR8rr, X86::OR8rm, 0 },
752 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
753 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
754 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
755 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
756 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
757 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
758 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
759 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
760 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
761 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
762 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
763 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
764 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
765 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
766 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
767 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
768 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
769 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
770 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
771 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
772 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
773 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
774 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
775 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
776 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
777 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
778 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
779 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
780 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
781 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
782 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
783 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
784 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
785 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
786 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
787 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
788 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
789 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
790 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
791 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
792 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
793 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
794 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
795 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
796 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
797 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
798 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
799 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
800 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
801 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
802 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
803 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
804 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
805 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
806 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
807 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
808 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
809 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
810 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
811 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
812 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
813 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
814 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
815 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
816 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
817 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
818 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
819 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
820 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
821 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
822 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
823 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
824 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
825 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
826 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
827 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
828 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
829 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
830 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
831 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
832 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
833 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
834 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
835 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
836 { X86::SBB32rr, X86::SBB32rm, 0 },
837 { X86::SBB64rr, X86::SBB64rm, 0 },
838 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
839 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
840 { X86::SUB16rr, X86::SUB16rm, 0 },
841 { X86::SUB32rr, X86::SUB32rm, 0 },
842 { X86::SUB64rr, X86::SUB64rm, 0 },
843 { X86::SUB8rr, X86::SUB8rm, 0 },
844 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
845 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
846 { X86::SUBSDrr, X86::SUBSDrm, 0 },
847 { X86::SUBSSrr, X86::SUBSSrm, 0 },
849 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
850 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
851 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
852 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
853 { X86::XOR16rr, X86::XOR16rm, 0 },
854 { X86::XOR32rr, X86::XOR32rm, 0 },
855 { X86::XOR64rr, X86::XOR64rm, 0 },
856 { X86::XOR8rr, X86::XOR8rm, 0 },
857 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
858 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
860 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
861 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
862 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
863 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
864 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
865 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
866 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
867 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
868 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
869 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
870 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
871 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
872 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
873 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
874 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
875 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
876 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
877 { X86::VADDPDrr, X86::VADDPDrm, 0 },
878 { X86::VADDPSrr, X86::VADDPSrm, 0 },
879 { X86::VADDSDrr, X86::VADDSDrm, 0 },
880 { X86::VADDSSrr, X86::VADDSSrm, 0 },
881 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
882 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
883 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
884 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
885 { X86::VANDPDrr, X86::VANDPDrm, 0 },
886 { X86::VANDPSrr, X86::VANDPSrm, 0 },
887 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
888 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
889 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
890 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
891 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
892 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
893 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
894 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
895 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
896 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
897 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
898 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
899 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
900 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
901 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
902 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
903 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
904 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
905 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
906 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
907 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
908 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
909 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
910 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
911 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
912 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
913 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
914 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
915 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
916 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
917 { X86::VMINPDrr, X86::VMINPDrm, 0 },
918 { X86::VMINPSrr, X86::VMINPSrm, 0 },
919 { X86::VMINSDrr, X86::VMINSDrm, 0 },
920 { X86::VMINSSrr, X86::VMINSSrm, 0 },
921 { X86::VMPSADBWrri, X86
922 { X86::VMULPDrr, X86::VMULPDrm, 0 },
923 { X86::VMULPSrr, X86::VMULPSrm, 0 },
924 { X86::VMULSDrr, X86::VMULSDrm, 0 },
925 { X86::VMULSSrr, X86::VMULSSrm, 0 },
926 { X86::VORPDrr, X86::VORPDrm, 0 },
927 { X86::VORPSrr, X86::VORPSrm, 0 },
928 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
929 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
930 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
931 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
932 { X86::VPADDBrr, X86::VPADDBrm, 0 },
933 { X86::VPADDDrr, X86::VPADDDrm, 0 },
934 { X86::VPADDQrr, X86::VPADDQrm, 0 },
935 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
936 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
937 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
938 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
939 { X86::VPADDWrr, X86::VPADDWrm, 0 },
940 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
941 { X86::VPANDNrr, X86::VPANDNrm, 0 },
942 { X86::VPANDrr, X86::VPANDrm, 0 },
943 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
944 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
945 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
946 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
947 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
948 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
949 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
950 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
951 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
952 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
953 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
954 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
955 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
956 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
957 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
958 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
959 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
960 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
961 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
962 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
963 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
964 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
965 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
966 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
967 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
968 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
969 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
970 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
971 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
972 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
973 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
974 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
975 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
976 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
977 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
978 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
979 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
980 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
981 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
982 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
983 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
984 { X86::VPORrr, X86::VPORrm, 0 },
985 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
986 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
987 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
988 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
989 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
990 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
991 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
992 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
993 { X86::VPSRADrr, X86::VPSRADrm, 0 },
994 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
995 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
996 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
997 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
998 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
999 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
1000 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1001 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
1002 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1003 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1004 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1005 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1006 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1007 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1008 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1009 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1010 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1011 { X86::VPXORrr, X86::VPXORrm, 0 },
1012 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1013 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1014 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1015 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
1016 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
1017 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
1018 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1019 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1020 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1021 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1022 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1023 { X86::VXORPSrr, X86::VXORPSrm, 0 },
1025 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1026 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1027 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1028 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1029 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1030 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1031 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1032 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1033 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1034 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1035 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1036 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1037 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1038 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1039 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1040 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
1041 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1042 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1043 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1044 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1045 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1046 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
1047 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
1048 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
1049 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
1050 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1051 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1052 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1053 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1054 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1055 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1056 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1057 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1058 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1059 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1060 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1061 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1062 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1063 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1064 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1065 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1066 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
1068 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1069 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1070 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1071 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1072 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1073 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1074 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1075 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1076 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1077 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1078 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1079 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1080 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1081 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1082 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1083 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1084 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1085 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1086 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1087 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
1088 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1089 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1090 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1091 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1092 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1093 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1094 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1095 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1096 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1097 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1098 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
1099 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
1100 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
1101 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
1102 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1103 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1104 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1105 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1106 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1107 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1108 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1109 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1110 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1111 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1112 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1113 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1114 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1115 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1116 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1117 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1118 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1119 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1120 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1121 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1122 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1123 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1124 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1125 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1126 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1127 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1128 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1129 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1130 { X86::VPORYrr, X86::VPORYrm, 0 },
1131 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1132 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1133 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
1134 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
1135 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
1136 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1137 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1138 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1139 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1140 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1141 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1142 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1143 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1144 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1145 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1146 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1147 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1148 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1149 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1150 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1151 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1152 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1153 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1154 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1155 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
1156 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1157 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
1158 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1159 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1160 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1161 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1162 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1163 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1164 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1165 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1166 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1167 { X86::VPXORYrr, X86::VPXORYrm, 0 },
1171 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 },
1172 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 },
1173 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 },
1174 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 },
1175 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 },
1176 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 },
1177 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 },
1178 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 },
1179 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 },
1180 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 },
1181 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 },
1182 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 },
1183 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 },
1184 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 },
1185 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 },
1186 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 },
1187 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 },
1188 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 },
1189 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 },
1190 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 },
1191 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 },
1192 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 },
1193 { X86::VFNMSUBPS4rrY, X86
1194 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 },
1195 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 },
1196 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 },
1197 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 },
1198 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 },
1199 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 },
1200 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 },
1201 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 },
1202 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 },
1205 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1206 { X86::ANDN64rr, X86::ANDN64rm, 0 },
1207 { X86::MULX32rr, X86::MULX32rm, 0 },
1208 { X86::MULX64rr, X86::MULX64rm, 0 },
1209 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1210 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1211 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1212 { X86::PEXT64rr, X86::PEXT64rm, 0 },
1215 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1216 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1217 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1218 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1219 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1220 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1221 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1222 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1223 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1224 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1225 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1226 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
1227 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1228 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
1229 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1230 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
1231 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1232 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1233 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1234 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1235 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1236 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1237 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1238 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1239 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
1240 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1241 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1242 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1243 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1244 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
1245 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1246 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
1247 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1248 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
1249 { X86::VALIGNQrri, X86::VALIGNQrmi, 0 },
1250 { X86::VALIGNDrri, X86::VALIGNDrmi, 0 },
1251 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
1254 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1255 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1256 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1257 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
1258 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, TB_ALIGN_16 },
1259 { X86::VAESDECrr, X86::VAESDECrm, TB_ALIGN_16 },
1260 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, TB_ALIGN_16 },
1261 { X86::VAESENCrr, X86::VAESENCrm, TB_ALIGN_16 },
1264 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1265 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1266 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1267 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1268 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1269 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
1270 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 },
1285 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
1286 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
1287 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
1288 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
1289 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
1290 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
1292 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1293 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1294 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1295 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1296 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1297 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1298 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1299 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1300 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1301 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1302 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1303 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
1305 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
1306 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
1307 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
1308 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
1309 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
1310 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
1312 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1313 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1314 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1315 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1316 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1317 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1318 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1319 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1320 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1321 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1322 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1323 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
1325 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
1326 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
1327 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
1328 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
1329 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
1330 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
1332 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1333 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1334 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1335 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1336 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1337 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1338 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1339 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1340 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1341 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1342 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1343 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
1345 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
1346 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
1347 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
1348 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
1349 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
1350 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
1352 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1353 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1354 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1355 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1356 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1357 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1358 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1359 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1360 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1361 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1362 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1363 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
1365 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1366 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1367 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1368 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1369 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1370 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1371 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1372 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1373 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1374 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1375 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1376 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
1378 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1379 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1380 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1381 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1382 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1383 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1384 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1385 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1386 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1387 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1388 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1389 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
1392 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 },
1393 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 },
1394 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 },
1395 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 },
1396 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 },
1397 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 },
1398 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 },
1399 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 },
1400 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 },
1401 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 },
1402 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 },
1403 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 },
1404 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 },
1405 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 },
1406 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 },
1407 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 },
1408 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 },
1409 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 },
1410 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 },
1411 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 },
1412 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 },
1413 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 },
1414 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 },
1415 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 },
1416 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 },
1417 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 },
1418 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 },
1419 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 },
1420 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 },
1421 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 },
1422 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 },
1423 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 },
1425 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1426 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1427 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1428 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
1429 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1430 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1431 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
1432 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 }
1468 case X86::MOVSX16rr8:
1469 case X86::MOVZX16rr8:
1470 case X86::MOVSX32rr8:
1471 case X86::MOVZX32rr8:
1472 case X86::MOVSX64rr8:
1477 case X86::MOVSX32rr16:
1478 case X86::MOVZX32rr16:
1479 case X86::MOVSX64rr16:
1480 case X86::MOVSX64rr32: {
1488 case X86::MOVSX16rr8:
1489 case X86::MOVZX16rr8:
1490 case X86::MOVSX32rr8:
1491 case X86::MOVZX32rr8:
1492 case X86::MOVSX64rr8:
1493 SubIdx = X86::sub_8bit;
1495 case X86::MOVSX32rr16:
1496 case X86::MOVZX32rr16:
1497 case X86::MOVSX64rr16:
1498 SubIdx = X86::sub_16bit;
1500 case X86::MOVSX64rr32:
1501 SubIdx = X86::sub_32bit;
1514 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
1515 MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
1516 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
1517 MI->getOperand(Op+X86::AddrDisp).isImm() &&
1518 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
1519 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
1520 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
1521 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
1531 case X86::MOV8rm:
1532 case X86::MOV16rm:
1533 case X86::MOV32rm:
1534 case X86::MOV64rm:
1535 case X86::LD_Fp64m:
1536 case X86::MOVSSrm:
1537 case X86::MOVSDrm:
1538 case X86::MOVAPSrm:
1539 case X86::MOVAPDrm:
1540 case X86::MOVDQArm:
1541 case X86::VMOVSSrm:
1542 case X86::VMOVSDrm:
1543 case X86::VMOVAPSrm:
1544 case X86::VMOVAPDrm:
1545 case X86::VMOVDQArm:
1546 case X86::VMOVAPSYrm:
1547 case X86::VMOVAPDYrm:
1548 case X86::VMOVDQAYrm:
1549 case X86::MMX_MOVD64rm:
1550 case X86::MMX_MOVQ64rm:
1551 case X86::VMOVAPSZrm:
1552 case X86::VMOVUPSZrm:
1560 case X86::MOV8mr:
1561 case X86::MOV16mr:
1562 case X86::MOV32mr:
1563 case X86::MOV64mr:
1564 case X86::ST_FpP64m:
1565 case X86::MOVSSmr:
1566 case X86::MOVSDmr:
1567 case X86::MOVAPSmr:
1568 case X86::MOVAPDmr:
1569 case X86::MOVDQAmr:
1570 case X86::VMOVSSmr:
1571 case X86::VMOVSDmr:
1572 case X86::VMOVAPSmr:
1573 case X86::VMOVAPDmr:
1574 case X86::VMOVDQAmr:
1575 case X86::VMOVAPSYmr:
1576 case X86::VMOVAPDYmr:
1577 case X86::VMOVDQAYmr:
1578 case X86::VMOVUPSZmr:
1579 case X86::VMOVAPSZmr:
1580 case X86::MMX_MOVD64mr:
1581 case X86::MMX_MOVQ64mr:
1582 case X86::MMX_MOVNTQmr:
1612 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1614 return MI->getOperand(X86::AddrNumOperands).getReg();
1632 /// X86::MOVPC32r.
1641 if (DefMI->getOpcode() != X86::MOVPC32r)
1654 case X86::MOV8rm:
1655 case X86::MOV16rm:
1656 case X86::MOV32rm:
1657 case X86::MOV64rm:
1658 case X86::LD_Fp64m:
1659 case X86::MOVSSrm:
1660 case X86::MOVSDrm:
1661 case X86::MOVAPSrm:
1662 case X86::MOVUPSrm:
1663 case X86::MOVAPDrm:
1664 case X86::MOVDQArm:
1665 case X86::MOVDQUrm:
1666 case X86::VMOVSSrm:
1667 case X86::VMOVSDrm:
1668 case X86::VMOVAPSrm:
1669 case X86::VMOVUPSrm:
1670 case X86::VMOVAPDrm:
1671 case X86::VMOVDQArm:
1672 case X86::VMOVDQUrm:
1673 case X86::VMOVAPSYrm:
1674 case X86::VMOVUPSYrm:
1675 case X86::VMOVAPDYrm:
1676 case X86::VMOVDQAYrm:
1677 case X86::VMOVDQUYrm:
1678 case X86::MMX_MOVD64rm:
1679 case X86::MMX_MOVQ64rm:
1680 case X86::FsVMOVAPSrm:
1681 case X86::FsVMOVAPDrm:
1682 case X86::FsMOVAPSrm:
1683 case X86::FsMOVAPDrm: {
1685 if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
1686 MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1687 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1688 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1690 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
1691 if (BaseReg == 0 || BaseReg == X86::RIP)
1694 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
1703 case X86::LEA32r:
1704 case X86::LEA64r: {
1705 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1706 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1707 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1708 !MI->getOperand(1+X86::AddrDisp).isReg()) {
1710 if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
1712 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
1741 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1745 if (MO.getReg() == X86::EFLAGS) {
1766 if ((*SI)->isLiveIn(X86::EFLAGS))
1777 return !MBB.isLiveIn(X86::EFLAGS);
1789 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1791 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1815 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
1817 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
1834 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1869 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1871 RC = Opc != X86::LEA32r ?
1872 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1878 if (Opc != X86::LEA64_32r) {
1921 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1949 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1952 Opc = X86::LEA64_32r;
1953 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1955 Opc = X86::LEA32r;
1956 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1965 // least on modern x86 machines).
1966 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1969 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1976 case X86::SHL16ri: {
1982 case X86::INC16r:
1983 case X86::INC64_16r:
1986 case X86::DEC16r:
1987 case X86::DEC64_16r:
1990 case X86::ADD16ri:
1991 case X86::ADD16ri8:
1992 case X86::ADD16ri_DB:
1993 case X86::ADD16ri8_DB:
1996 case X86::ADD16rr:
1997 case X86::ADD16rr_DB: {
2008 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2010 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2013 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2016 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2030 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2048 /// three-address instruction on demand. This allows the X86 target (for
2081 case X86::SHUFPSrri: {
2089 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2093 case X86::SHUFPDrri: {
2105 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2109 case X86::SHL64ri: {
2117 &X86::GR64_NOSPRegClass))
2120 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2125 case X86::SHL32ri: {
2130 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2151 case X86::SHL16ri: {
2158 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2167 case X86::INC64r:
2168 case X86::INC32r:
2169 case X86::INC64_32r: {
2171 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2172 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2189 case X86::INC16r:
2190 case X86::INC64_16r:
2195 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2198 case X86::DEC64r:
2199 case X86::DEC32r:
2200 case X86::DEC64_32r: {
2202 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2203 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2222 case X86::DEC16r:
2223 case X86::DEC64_16r:
2228 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2231 case X86::ADD64rr:
2232 case X86::ADD64rr_DB:
2233 case X86::ADD32rr:
2234 case X86::ADD32rr_DB: {
2237 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2238 Opc = X86::LEA64r;
2240 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2274 case X86::ADD16rr:
2275 case X86::ADD16rr_DB: {
2282 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2296 case X86::ADD64ri32:
2297 case X86::ADD64ri8:
2298 case X86::ADD64ri32_DB:
2299 case X86::ADD64ri8_DB:
2301 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2305 case X86::ADD32ri:
2306 case X86::ADD32ri8:
2307 case X86::ADD32ri_DB:
2308 case X86::ADD32ri8_DB: {
2310 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2328 case X86::ADD16ri:
2329 case X86::ADD16ri8:
2330 case X86::ADD16ri_DB:
2331 case X86::ADD16ri8_DB:
2336 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2363 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2364 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2365 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2366 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2367 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2368 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2373 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2374 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2375 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2376 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2377 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2378 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2390 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
2391 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2392 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
2393 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2394 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2395 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
2396 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
2397 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2398 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2399 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
2400 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
2401 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2402 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
2403 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2404 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
2405 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2409 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
2410 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
2411 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
2412 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2413 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2414 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2415 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
2416 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
2417 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
2418 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2419 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2420 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2421 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2422 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2423 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2424 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
2425 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
2426 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
2427 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
2428 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
2429 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
2430 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2431 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2432 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2433 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2434 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2435 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2436 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
2437 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
2438 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
2439 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
2440 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
2441 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
2442 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2443 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2444 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2445 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
2446 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
2447 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
2448 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2449 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2450 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2451 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
2452 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
2453 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
2454 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2455 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2456 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2474 case X86::VFMADDPDr231r:
2475 case X86::VFMADDPSr231r:
2476 case X86::VFMADDSDr231r:
2477 case X86::VFMADDSSr231r:
2478 case X86::VFMSUBPDr231r:
2479 case X86::VFMSUBPSr231r:
2480 case X86::VFMSUBSDr231r:
2481 case X86::VFMSUBSSr231r:
2482 case X86::VFNMADDPDr231r:
2483 case X86::VFNMADDPSr231r:
2484 case X86::VFNMADDSDr231r:
2485 case X86::VFNMADDSSr231r:
2486 case X86::VFNMSUBPDr231r:
2487 case X86::VFNMSUBPSr231r:
2488 case X86::VFNMSUBSDr231r:
2489 case X86::VFNMSUBSSr231r:
2490 case X86::VFMADDPDr231rY:
2491 case X86::VFMADDPSr231rY:
2492 case X86::VFMSUBPDr231rY:
2493 case X86::VFMSUBPSr231rY:
2494 case X86::VFNMADDPDr231rY:
2495 case X86::VFNMADDPSr231rY:
2496 case X86::VFNMSUBPDr231rY:
2497 case X86::VFNMSUBPSr231rY:
2506 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2508 default: return X86::COND_INVALID;
2509 case X86::JE_4: return X86::COND_E;
2510 case X86::JNE_4: return X86::COND_NE;
2511 case X86::JL_4: return X86::COND_L;
2512 case X86::JLE_4: return X86::COND_LE;
2513 case X86::JG_4: return X86::COND_G;
2514 case X86::JGE_4: return X86::COND_GE;
2515 case X86::JB_4: return X86::COND_B;
2516 case X86::JBE_4: return X86::COND_BE;
2517 case X86::JA_4: return X86::COND_A;
2518 case X86::JAE_4: return X86::COND_AE;
2519 case X86::JS_4: return X86::COND_S;
2520 case X86::JNS_4: return X86::COND_NS;
2521 case X86::JP_4: return X86::COND_P;
2522 case X86::JNP_4: return X86::COND_NP;
2523 case X86::JO_4: return X86::COND_O;
2524 case X86::JNO_4: return X86::COND_NO;
2529 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2531 default: return X86::COND_INVALID;
2532 case X86::SETAr: case X86::SETAm: return X86::COND_A;
2533 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2534 case X86::SETBr: case X86::SETBm: return X86::COND_B;
2535 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2536 case X86::SETEr: case X86::SETEm: return X86::COND_E;
2537 case X86::SETGr: case X86::SETGm: return X86::COND_G;
2538 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2539 case X86::SETLr: case X86::SETLm: return X86::COND_L;
2540 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2541 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2542 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2543 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2544 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2545 case X86::SETOr: case X86::SETOm: return X86::COND_O;
2546 case X86::SETPr: case X86::SETPm: return X86::COND_P;
2547 case X86::SETSr: case X86::SETSm: return X86::COND_S;
2552 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2554 default: return X86::COND_INVALID;
2555 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
2556 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
2557 return X86::COND_A;
2558 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2559 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2560 return X86::COND_AE;
2561 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
2562 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
2563 return X86::COND_B;
2564 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2565 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2566 return X86::COND_BE;
2567 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
2568 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
2569 return X86::COND_E;
2570 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
2571 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
2572 return X86::COND_G;
2573 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2574 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2575 return X86::COND_GE;
2576 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
2577 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
2578 return X86::COND_L;
2579 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2580 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2581 return X86::COND_LE;
2582 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2583 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2584 return X86::COND_NE;
2585 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2586 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2587 return X86::COND_NO;
2588 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2589 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2590 return X86::COND_NP;
2591 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2592 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2593 return X86::COND_NS;
2594 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
2595 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
2596 return X86::COND_O;
2597 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
2598 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
2599 return X86::COND_P;
2600 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
2601 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
2602 return X86::COND_S;
2606 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2609 case X86::COND_E: return X86::JE_4;
2610 case X86::COND_NE: return X86::JNE_4;
2611 case X86::COND_L: return X86::JL_4;
2612 case X86::COND_LE: return X86::JLE_4;
2613 case X86::COND_G: return X86::JG_4;
2614 case X86::COND_GE: return X86::JGE_4;
2615 case X86::COND_B: return X86::JB_4;
2616 case X86::COND_BE: return X86::JBE_4;
2617 case X86::COND_A: return X86::JA_4;
2618 case X86::COND_AE: return X86::JAE_4;
2619 case X86::COND_S: return X86::JS_4;
2620 case X86::COND_NS: return X86::JNS_4;
2621 case X86::COND_P: return X86::JP_4;
2622 case X86::COND_NP: return X86::JNP_4;
2623 case X86::COND_O: return X86::JO_4;
2624 case X86::COND_NO: return X86::JNO_4;
2630 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2633 case X86::COND_E: return X86::COND_NE;
2634 case X86::COND_NE: return X86::COND_E;
2635 case X86::COND_L: return X86::COND_GE;
2636 case X86::COND_LE: return X86::COND_G;
2637 case X86::COND_G: return X86::COND_LE;
2638 case X86::COND_GE: return X86::COND_L;
2639 case X86::COND_B: return X86::COND_AE;
2640 case X86::COND_BE: return X86::COND_A;
2641 case X86::COND_A: return X86::COND_BE;
2642 case X86::COND_AE: return X86::COND_B;
2643 case X86::COND_S: return X86::COND_NS;
2644 case X86::COND_NS: return X86::COND_S;
2645 case X86::COND_P: return X86::COND_NP;
2646 case X86::COND_NP: return X86::COND_P;
2647 case X86::COND_O: return X86::COND_NO;
2648 case X86::COND_NO: return X86::COND_O;
2655 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2657 default: return X86::COND_INVALID;
2658 case X86::COND_E: return X86::COND_E;
2659 case X86::COND_NE: return X86::COND_NE;
2660 case X86::COND_L: return X86::COND_G;
2661 case X86::COND_LE: return X86::COND_GE;
2662 case X86::COND_G: return X86::COND_L;
2663 case X86::COND_GE: return X86::COND_LE;
2664 case X86::COND_B: return X86::COND_A;
2665 case X86::COND_BE: return X86::COND_AE;
2666 case X86::COND_A: return X86::COND_B;
2667 case X86::COND_AE: return X86::COND_BE;
2673 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
2675 { X86::SETAr, X86::SETAm },
2676 { X86::SETAEr, X86::SETAEm },
2677 { X86::SETBr, X86::SETBm },
2678 { X86::SETBEr, X86::SETBEm },
2679 { X86::SETEr, X86::SETEm },
2680 { X86::SETGr, X86::SETGm },
2681 { X86::SETGEr, X86::SETGEm },
2682 { X86::SETLr, X86::SETLm },
2683 { X86::SETLEr, X86::SETLEm },
2684 { X86::SETNEr, X86::SETNEm },
2685 { X86::SETNOr, X86::SETNOm },
2686 { X86::SETNPr, X86::SETNPm },
2687 { X86::SETNSr, X86::SETNSm },
2688 { X86::SETOr, X86::SETOm },
2689 { X86::SETPr, X86::SETPm },
2690 { X86::SETSr, X86::SETSm }
2699 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
2702 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
2703 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2704 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
2705 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2706 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
2707 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
2708 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2709 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
2710 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2711 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2712 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2713 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2714 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2715 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
2716 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
2717 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
2718 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
2719 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2720 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
2721 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2722 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
2723 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
2724 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2725 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
2726 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2727 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2728 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2729 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2730 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2731 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
2732 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
2733 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
2782 if (I->getOpcode() == X86::JMP_4) {
2812 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
2813 if (BranchCode == X86::COND_INVALID)
2844 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2874 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2881 if ((OldBranchCode == X86::COND_NP &&
2882 BranchCode == X86::COND_E) ||
2883 (OldBranchCode == X86::COND_E &&
2884 BranchCode == X86::COND_NP))
2885 BranchCode = X86::COND_NP_OR_E;
2886 else if ((OldBranchCode == X86::COND_P &&
2887 BranchCode == X86::COND_NE) ||
2888 (OldBranchCode == X86::COND_NE &&
2889 BranchCode == X86::COND_P))
2890 BranchCode = X86::COND_NE_OR_P;
2909 if (I->getOpcode() != X86::JMP_4 &&
2910 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2929 "X86 branch conditions have one component!");
2934 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2940 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2942 case X86::COND_NP_OR_E:
2944 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2946 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2949 case X86::COND_NE_OR_P:
2951 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2953 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2964 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2981 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
2992 if (X86::GR16RegClass.hasSubClassEq(RC) ||
2993 X86::GR32RegClass.hasSubClassEq(RC) ||
2994 X86::GR64RegClass.hasSubClassEq(RC)) {
3014 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
3022 return X86::GR8_ABCD_HRegClass.contains(Reg);
3036 if (X86::GR64RegClass.contains(DestReg)) {
3037 if (X86::VR128XRegClass.contains(SrcReg))
3039 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3040 X86::MOVPQIto64rr);
3041 if (X86::VR64RegClass.contains(SrcReg))
3043 return X86::MOVSDto64rr;
3044 } else if (X86::GR64RegClass.contains(SrcReg)) {
3046 if (X86::VR128XRegClass.contains(DestReg))
3047 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3048 X86::MOV64toPQIrr);
3050 if (X86::VR64RegClass.contains(DestReg))
3051 return X86::MOV64toSDrr;
3057 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3059 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3061 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3063 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3068 return X86::VK8RegClass.contains(Reg) ||
3069 X86::VK16RegClass.contains(Reg) ||
3070 X86::VK1RegClass.contains(Reg);
3074 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3075 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3076 X86::VR512RegClass.contains(DestReg, SrcReg)) {
3079 return X86::VMOVAPSZrr;
3083 return X86::KMOVWkk;
3085 (X86::GR32RegClass.contains(SrcReg) ||
3086 X86::GR16RegClass.contains(SrcReg) ||
3087 X86::GR8RegClass.contains(SrcReg))) {
3089 return X86::KMOVWkr;
3091 if ((X86::GR32RegClass.contains(DestReg) ||
3092 X86::GR16RegClass.contains(DestReg) ||
3093 X86::GR8RegClass.contains(DestReg)) &&
3096 return X86::KMOVWrk;
3109 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3110 Opc = X86::MOV64rr;
3111 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3112 Opc = X86::MOV32rr;
3113 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3114 Opc = X86::MOV16rr;
3115 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3116 // Copying to or from a physical H register on x86-64 requires a NOREX
3120 Opc = X86::MOV8rr_NOREX;
3122 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3125 Opc = X86::MOV8rr;
3127 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3128 Opc = X86::MMX_MOVQ64rr;
3131 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3132 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3133 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3134 Opc = X86::VMOVAPSYrr;
3147 if (SrcReg == X86::EFLAGS) {
3148 if (X86::GR64RegClass.contains(DestReg)) {
3149 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3150 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3153 if (X86::GR32RegClass.contains(DestReg)) {
3154 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3155 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3159 if (DestReg == X86::EFLAGS) {
3160 if (X86::GR64RegClass.contains(SrcReg)) {
3161 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3163 BuildMI(MBB, MI, DL, get(X86::POPF64));
3166 if (X86::GR32RegClass.contains(SrcReg)) {
3167 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3169 BuildMI(MBB, MI, DL, get(X86::POPF32));
3185 if (X86::VK8RegClass.hasSubClassEq(RC) ||
3186 X86::VK16RegClass.hasSubClassEq(RC))
3187 return load ? X86::KMOVWkm : X86::KMOVWmk;
3188 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3189 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3190 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3191 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3192 if (X86::VR512RegClass.hasSubClassEq(RC))
3193 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3201 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3203 // Copying to or from a physical H register on x86-64 requires a NOREX
3205 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3206 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3207 return load ? X86::MOV8rm : X86::MOV8mr;
3209 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3210 return load ? X86::MOV16rm : X86::MOV16mr;
3212 if (X86::GR32RegClass.hasSubClassEq(RC))
3213 return load ? X86::MOV32rm : X86::MOV32mr;
3214 if (X86::FR32RegClass.hasSubClassEq(RC))
3216 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3217 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3218 if (X86::RFP32RegClass.hasSubClassEq(RC))
3219 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3222 if (X86::GR64RegClass.hasSubClassEq(RC))
3223 return load ? X86::MOV64rm : X86::MOV64mr;
3224 if (X86::FR64RegClass.hasSubClassEq(RC))
3226 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3227 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3228 if (X86
3229 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3230 if (X86::RFP64RegClass.hasSubClassEq(RC))
3231 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3234 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3235 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3237 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3238 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
3242 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3243 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
3246 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3247 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3250 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3251 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
3254 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3256 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3258 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3260 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3262 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3358 case X86::CMP64ri32:
3359 case X86::CMP64ri8:
3360 case X86::CMP32ri:
3361 case X86::CMP32ri8:
3362 case X86::CMP16ri:
3363 case X86::CMP16ri8:
3364 case X86::CMP8ri:
3371 case X86::SUB64rm:
3372 case X86::SUB32rm:
3373 case X86::SUB16rm:
3374 case X86::SUB8rm:
3380 case X86::SUB64rr:
3381 case X86::SUB32rr:
3382 case X86::SUB16rr:
3383 case X86::SUB8rr:
3389 case X86::SUB64ri32:
3390 case X86::SUB64ri8:
3391 case X86::SUB32ri:
3392 case X86::SUB32ri8:
3393 case X86::SUB16ri:
3394 case X86::SUB16ri8:
3395 case X86::SUB8ri:
3401 case X86::CMP64rr:
3402 case X86::CMP32rr:
3403 case X86::CMP16rr:
3404 case X86::CMP8rr:
3410 case X86::TEST8rr:
3411 case X86::TEST16rr:
3412 case X86::TEST32rr:
3413 case X86::TEST64rr:
3434 if (((FlagI->getOpcode() == X86::CMP64rr &&
3435 OI->getOpcode() == X86::SUB64rr) ||
3436 (FlagI->getOpcode() == X86::CMP32rr &&
3437 OI->getOpcode() == X86::SUB32rr)||
3438 (FlagI->getOpcode() == X86::CMP16rr &&
3439 OI->getOpcode() == X86::SUB16rr)||
3440 (FlagI->getOpcode() == X86::CMP8rr &&
3441 OI->getOpcode() == X86::SUB8rr)) &&
3448 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3449 OI->getOpcode() == X86::SUB64ri32) ||
3450 (FlagI->getOpcode() == X86::CMP64ri8 &&
3451 OI->getOpcode() == X86::SUB64ri8) ||
3452 (FlagI->getOpcode() == X86::CMP32ri &&
3453 OI->getOpcode() == X86::SUB32ri) ||
3454 (FlagI->getOpcode() == X86::CMP32ri8 &&
3455 OI->getOpcode() == X86::SUB32ri8) ||
3456 (FlagI->getOpcode() == X86::CMP16ri &&
3457 OI->getOpcode() == X86::SUB16ri) ||
3458 (FlagI->getOpcode() == X86::CMP16ri8 &&
3459 OI->getOpcode() == X86::SUB16ri8) ||
3460 (FlagI->getOpcode() == X86::CMP8ri &&
3461 OI->getOpcode() == X86::SUB8ri)) &&
3476 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
3477 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
3482 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
3488 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3489 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3492 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3493 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3494 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3495 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3496 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
3497 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
3498 case X86::DEC64_32r: case X86::DEC64_16r:
3499 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3500 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3501 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3502 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3503 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
3504 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
3505 case X86::INC64_32r: case X86::INC64_16r:
3506 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3507 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3508 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3509 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3510 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3511 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3512 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3513 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3514 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3515 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3516 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3517 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3518 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3519 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3520 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
3521 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
3522 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
3523 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
3524 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
3525 case X86::ADC32ri: case X86::ADC32ri8:
3526 case X86::ADC32rr: case X86::ADC64ri32:
3527 case X86::ADC64ri8: case X86::ADC64rr:
3528 case X86::SBB32ri: case X86::SBB32ri8:
3529 case X86::SBB32rr: case X86::SBB64ri32:
3530 case X86::SBB64ri8: case X86::SBB64rr:
3531 case X86::ANDN32rr: case X86::ANDN32rm:
3532 case X86::ANDN64rr: case X86::ANDN64rm:
3533 case X86::BEXTR32rr: case X86::BEXTR64rr:
3534 case X86::BEXTR32rm: case X86::BEXTR64rm:
3535 case X86::BLSI32rr: case X86::BLSI32rm:
3536 case X86::BLSI64rr: case X86::BLSI64rm:
3537 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3538 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3539 case X86::BLSR32rr: case X86::BLSR32rm:
3540 case X86::BLSR64rr: case X86::BLSR64rm:
3541 case X86::BZHI32rr: case X86::BZHI32rm:
3542 case X86::BZHI64rr: case X86::BZHI64rm:
3543 case X86::LZCNT16rr: case X86::LZCNT16rm:
3544 case X86::LZCNT32rr: case X86::LZCNT32rm:
3545 case X86::LZCNT64rr: case X86::LZCNT64rm:
3546 case X86::POPCNT16rr:case X86::POPCNT16rm:
3547 case X86::POPCNT32rr:case X86::POPCNT32rm:
3548 case X86::POPCNT64rr:case X86::POPCNT64rm:
3549 case X86::TZCNT16rr: case X86::TZCNT16rm:
3550 case X86::TZCNT32rr: case X86::TZCNT32rm:
3551 case X86::TZCNT64rr: case X86::TZCNT64rm:
3558 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
3560 default: return X86::COND_INVALID;
3561 case X86::LZCNT16rr: case X86::LZCNT16rm:
3562 case X86::LZCNT32rr: case X86::LZCNT32rm:
3563 case X86::LZCNT64rr: case X86::LZCNT64rm:
3564 return X86::COND_B;
3565 case X86::POPCNT16rr:case X86::POPCNT16rm:
3566 case X86::POPCNT32rr:case X86::POPCNT32rm:
3567 case X86::POPCNT64rr:case X86::POPCNT64rm:
3568 return X86::COND_E;
3569 case X86::TZCNT16rr: case X86::TZCNT16rm:
3570 case X86::TZCNT32rr: case X86::TZCNT32rm:
3571 case X86::TZCNT64rr: case X86::TZCNT64rm:
3572 return X86::COND_B;
3587 case X86::SUB64ri32:
3588 case X86::SUB64ri8:
3589 case X86::SUB32ri:
3590 case X86::SUB32ri8:
3591 case X86::SUB16ri:
3592 case X86::SUB16ri8:
3593 case X86::SUB8ri:
3594 case X86::SUB64rm:
3595 case X86::SUB32rm:
3596 case X86::SUB16rm:
3597 case X86::SUB8rm:
3598 case X86::SUB64rr:
3599 case X86::SUB32rr:
3600 case X86::SUB16rr:
3601 case X86::SUB8rr: {
3607 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3608 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3609 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3610 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3611 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3612 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3613 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3614 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3615 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3616 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3617 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3618 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3619 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3620 case X86X86::CMP16ri8; break;
3621 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3626 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3627 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3649 X86::CondCode NewCC = X86::COND_INVALID;
3656 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3658 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3696 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3697 Instr->readsRegister(X86::EFLAGS, TRI)) {
3703 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
3704 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3730 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3731 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3742 X86::CondCode OldCC = X86::COND_INVALID;
3750 if (OldCC != X86::COND_INVALID)
3753 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3755 if (OldCC == X86::COND_INVALID) return false;
3760 case X86::COND_A: case X86::COND_AE:
3761 case X86::COND_B: case X86::COND_BE:
3762 case X86::COND_G: case X86::COND_GE:
3763 case X86::COND_L: case X86::COND_LE:
3764 case X86::COND_O: case X86::COND_NO:
3775 case X86::COND_E:
3777 case X86::COND_NE:
3786 if (NewCC == X86::COND_INVALID) return false;
3808 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3821 if ((*SI)->isLiveIn(X86::EFLAGS))
3836 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3837 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3852 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3968 case X86::MOV32r0:
3969 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
3970 case X86::SETB_C8r:
3971 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
3972 case X86::SETB_C16r:
3973 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
3974 case X86::SETB_C32r:
3975 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
3976 case X86::SETB_C64r:
3977 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
3978 case X86::V_SET0:
3979 case X86::FsFLD0SS:
3980 case X86::FsFLD0SD:
3981 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
3982 case X86::AVX_SET0:
3984 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
3985 case X86::AVX512_512_SET0:
3986 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
3987 case X86::V_SETALLONES:
3988 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
3989 case X86::AVX2_SETALLONES:
3990 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
3991 case X86::TEST8ri_NOREX:
3992 MI->setDesc(get(X86::TEST8ri));
3994 case X86::KSET0B:
3995 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
3996 case X86::KSET1B:
3997 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
4082 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
4092 if (MI->getOpcode() == X86::ADD32ri &&
4107 if (MI->getOpcode() == X86::MOV32r0) {
4108 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4138 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4145 Opcode = X86::MOV32rm;
4162 X86::sub_32bit));
4164 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4194 case X86::CVTSI2SSrr:
4195 case X86::CVTSI2SS64rr:
4196 case X86::CVTSI2SDrr:
4197 case X86::CVTSI2SD64rr:
4198 case X86::CVTSD2SSrr:
4199 case X86::Int_CVTSD2SSrr:
4200 case X86::CVTSS2SDrr:
4201 case X86::Int_CVTSS2SDrr:
4202 case X86::RCPSSr:
4203 case X86::RCPSSr_Int:
4204 case X86::ROUNDSDr:
4205 case X86::ROUNDSDr_Int:
4206 case X86::ROUNDSSr:
4207 case X86::ROUNDSSr_Int:
4208 case X86::RSQRTSSr:
4209 case X86::RSQRTSSr_Int:
4210 case X86::SQRTSSr:
4211 case X86::SQRTSSr_Int:
4247 case X86::VCVTSI2SSrr:
4248 case X86::Int_VCVTSI2SSrr:
4249 case X86::VCVTSI2SS64rr:
4250 case X86::Int_VCVTSI2SS64rr:
4251 case X86::VCVTSI2SDrr:
4252 case X86::Int_VCVTSI2SDrr:
4253 case X86::VCVTSI2SD64rr:
4254 case X86::Int_VCVTSI2SD64rr:
4255 case X86::VCVTSD2SSrr:
4256 case X86::Int_VCVTSD2SSrr:
4257 case X86::VCVTSS2SDrr:
4258 case X86::Int_VCVTSS2SDrr:
4259 case X86::VRCPSSr:
4260 case X86::VROUNDSDr:
4261 case X86::VROUNDSDr_Int:
4262 case X86::VROUNDSSr:
4263 case X86::VROUNDSSr_Int:
4264 case X86::VRSQRTSSr:
4265 case X86::VSQRTSSr:
4268 case X86::VCVTSD2SSZrr:
4269 case X86::VCVTSS2SDZrr:
4314 if (X86::VR128RegClass.contains(Reg)) {
4318 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
4321 } else if (X86::VR256RegClass.contains(Reg)) {
4324 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4325 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4360 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
4361 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4362 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4363 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
4406 case X86::AVX2_SETALLONES:
4407 case X86::AVX_SET0:
4410 case X86::V_SET0:
4411 case X86::V_SETALLONES:
4414 case X86::FsFLD0SD:
4417 case X86::FsFLD0SS:
4427 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
4428 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
4429 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
4430 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
4443 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
4445 case X86::V_SET0:
4446 case X86::V_SETALLONES:
4447 case X86::AVX2_SETALLONES:
4448 case X86::AVX_SET0:
4449 case X86::FsFLD0SD:
4450 case X86::FsFLD0SS: {
4459 // x86-32 PIC requires a PIC base register for constant pools.
4463 PICBase = X86::RIP;
4476 if (Opc == X86::FsFLD0SS)
4478 else if (Opc == X86::FsFLD0SD)
4480 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
4485 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
4499 if ((LoadMI->getOpcode() == X86::MOVSSrm ||
4500 LoadMI->getOpcode() == X86::VMOVSSrm) &&
4506 if ((LoadMI->getOpcode() == X86::MOVSDrm ||
4507 LoadMI->getOpcode() == X86::VMOVSDrm) &&
4515 X86::AddrNumOperands; i != NumOps; ++i)
4532 case X86::TEST8rr:
4533 case X86::TEST16rr:
4534 case X86::TEST32rr:
4535 case X86::TEST64rr:
4537 case X86::ADD32ri:
4563 if (Opc == X86::MOV32r0)
4601 RC == &X86::VR128RegClass &&
4607 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
4613 if (i >= Index && i < Index + X86::AddrNumOperands)
4632 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
4664 case X86::CMP64ri32:
4665 case X86::CMP64ri8:
4666 case X86::CMP32ri:
4667 case X86::CMP32ri8:
4668 case X86::CMP16ri:
4669 case X86::CMP16ri8:
4670 case X86::CMP8ri: {
4677 case X86::CMP64ri8:
4678 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
4679 case X86::CMP32ri8:
4680 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
4681 case X86::CMP16ri8:
4682 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
4683 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
4730 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
4749 RC == &X86::VR128RegClass &&
4792 RC == &X86::VR128RegClass &&
4838 case X86::MOV8rm:
4839 case X86::MOV16rm:
4840 case X86::MOV32rm:
4841 case X86::MOV64rm:
4842 case X86::LD_Fp32m:
4843 case X86::LD_Fp64m:
4844 case X86::LD_Fp80m:
4845 case X86::MOVSSrm:
4846 case X86::MOVSDrm:
4847 case X86::MMX_MOVD64rm:
4848 case X86::MMX_MOVQ64rm:
4849 case X86::FsMOVAPSrm:
4850 case X86::FsMOVAPDrm:
4851 case X86::MOVAPSrm:
4852 case X86::MOVUPSrm:
4853 case X86::MOVAPDrm:
4854 case X86::MOVDQArm:
4855 case X86::MOVDQUrm:
4857 case X86::VMOVSSrm:
4858 case X86::VMOVSDrm:
4859 case X86::FsVMOVAPSrm:
4860 case X86::FsVMOVAPDrm:
4861 case X86::VMOVAPSrm:
4862 case X86::VMOVUPSrm:
4863 case X86::VMOVAPDrm:
4864 case X86::VMOVDQArm:
4865 case X86::VMOVDQUrm:
4866 case X86::VMOVAPSYrm:
4867 case X86::VMOVUPSYrm:
4868 case X86::VMOVAPDYrm:
4869 case X86::VMOVDQAYrm:
4870 case X86::VMOVDQUYrm:
4875 case X86::MOV8rm:
4876 case X86::MOV16rm:
4877 case X86::MOV32rm:
4878 case X86::MOV64rm:
4879 case X86::LD_Fp32m:
4880 case X86::LD_Fp64m:
4881 case X86::LD_Fp80m:
4882 case X86::MOVSSrm:
4883 case X86::MOVSDrm:
4884 case X86::MMX_MOVD64rm:
4885 case X86::MMX_MOVQ64rm:
4886 case X86::FsMOVAPSrm:
4887 case X86::FsMOVAPDrm:
4888 case X86::MOVAPSrm:
4889 case X86::MOVUPSrm:
4890 case X86::MOVAPDrm:
4891 case X86::MOVDQArm:
4892 case X86::MOVDQUrm:
4894 case X86::VMOVSSrm:
4895 case X86::VMOVSDrm:
4896 case X86::FsVMOVAPSrm:
4897 case X86::FsVMOVAPDrm:
4898 case X86::VMOVAPSrm:
4899 case X86::VMOVUPSrm:
4900 case X86::VMOVAPDrm:
4901 case X86::VMOVDQArm:
4902 case X86::VMOVDQUrm:
4903 case X86::VMOVAPSYrm:
4904 case X86::VMOVUPSYrm:
4905 case X86::VMOVAPDYrm:
4906 case X86::VMOVDQAYrm:
4907 case X86::VMOVDQUYrm:
4949 case X86::LD_Fp32m:
4950 case X86::LD_Fp64m:
4951 case X86::LD_Fp80m:
4952 case X86::MMX_MOVD64rm:
4953 case X86::MMX_MOVQ64rm:
5000 case X86::JE_4:
5001 case X86::JNE_4:
5002 case X86::JL_4:
5003 case X86::JLE_4:
5004 case X86::JG_4:
5005 case X86::JGE_4:
5008 case X86::JB_4:
5009 case X86::JBE_4:
5010 case X86::JA_4:
5011 case X86::JAE_4:
5014 case X86::JS_4:
5015 case X86::JNS_4:
5016 case X86::JP_4:
5017 case X86::JNP_4:
5018 case X86::JO_4:
5019 case X86::JNO_4:
5026 case X86::TEST8rr:
5027 case X86::TEST16rr:
5028 case X86::TEST32rr:
5029 case X86::TEST64rr:
5030 case X86::TEST8ri:
5031 case X86::TEST16ri:
5032 case X86::TEST32ri:
5033 case X86::TEST32i32:
5034 case X86::TEST64i32:
5035 case X86::TEST64ri32:
5036 case X86::TEST8rm:
5037 case X86::TEST16rm:
5038 case X86::TEST32rm:
5039 case X86::TEST64rm:
5040 case X86
5041 case X86::AND16i16:
5042 case X86::AND16ri:
5043 case X86::AND16ri8:
5044 case X86::AND16rm:
5045 case X86::AND16rr:
5046 case X86::AND32i32:
5047 case X86::AND32ri:
5048 case X86::AND32ri8:
5049 case X86::AND32rm:
5050 case X86::AND32rr:
5051 case X86::AND64i32:
5052 case X86::AND64ri32:
5053 case X86::AND64ri8:
5054 case X86::AND64rm:
5055 case X86::AND64rr:
5056 case X86::AND8i8:
5057 case X86::AND8ri:
5058 case X86::AND8rm:
5059 case X86::AND8rr:
5061 case X86::CMP16i16:
5062 case X86::CMP16ri:
5063 case X86::CMP16ri8:
5064 case X86::CMP16rm:
5065 case X86::CMP16rr:
5066 case X86::CMP32i32:
5067 case X86::CMP32ri:
5068 case X86::CMP32ri8:
5069 case X86::CMP32rm:
5070 case X86::CMP32rr:
5071 case X86::CMP64i32:
5072 case X86::CMP64ri32:
5073 case X86::CMP64ri8:
5074 case X86::CMP64rm:
5075 case X86::CMP64rr:
5076 case X86::CMP8i8:
5077 case X86::CMP8ri:
5078 case X86::CMP8rm:
5079 case X86::CMP8rr:
5080 case X86::ADD16i16:
5081 case X86::ADD16ri:
5082 case X86::ADD16ri8:
5083 case X86::ADD16ri8_DB:
5084 case X86::ADD16ri_DB:
5085 case X86::ADD16rm:
5086 case X86::ADD16rr:
5087 case X86::ADD16rr_DB:
5088 case X86::ADD32i32:
5089 case X86::ADD32ri:
5090 case X86::ADD32ri8:
5091 case X86::ADD32ri8_DB:
5092 case X86::ADD32ri_DB:
5093 case X86::ADD32rm:
5094 case X86::ADD32rr:
5095 case X86::ADD32rr_DB:
5096 case X86::ADD64i32:
5097 case X86::ADD64ri32:
5098 case X86::ADD64ri32_DB:
5099 case X86::ADD64ri8:
5100 case X86::ADD64ri8_DB:
5101 case X86::ADD64rm:
5102 case X86::ADD64rr:
5103 case X86::ADD64rr_DB:
5104 case X86::ADD8i8:
5105 case X86::ADD8mi:
5106 case X86::ADD8mr:
5107 case X86::ADD8ri:
5108 case X86::ADD8rm:
5109 case X86::ADD8rr:
5110 case X86::SUB16i16:
5111 case X86::SUB16ri:
5112 case X86::SUB16ri8:
5113 case X86::SUB16rm:
5114 case X86::SUB16rr:
5115 case X86::SUB32i32:
5116 case X86::SUB32ri:
5117 case X86::SUB32ri8:
5118 case X86::SUB32rm:
5119 case X86::SUB32rr:
5120 case X86::SUB64i32:
5121 case X86::SUB64ri32:
5122 case X86::SUB64ri8:
5123 case X86::SUB64rm:
5124 case X86::SUB64rr:
5125 case X86::SUB8i8:
5126 case X86::SUB8ri:
5127 case X86::SUB8rm:
5128 case X86::SUB8rr:
5130 case X86::INC16r:
5131 case X86::INC32r:
5132 case X86::INC64_16r:
5133 case X86::INC64_32r:
5134 case X86::INC64r:
5135 case X86::INC8r:
5136 case X86::DEC16r:
5137 case X86::DEC32r:
5138 case X86::DEC64_16r:
5139 case X86::DEC64_32r:
5140 case X86::DEC64r:
5141 case X86::DEC8r:
5148 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5149 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5150 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5160 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5161 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
5172 "X86-64 PIC uses RIP relative addressing");
5182 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
5192 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
5193 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
5194 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
5195 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
5196 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
5197 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
5198 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
5199 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
5200 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
5201 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
5202 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
5203 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
5204 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
5205 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
5207 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
5208 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
5209 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
5210 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
5211 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
5212 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5213 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
5214 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
5215 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
5216 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
5217 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
5218 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
5219 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
5220 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
5222 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
5223 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
5224 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
5225 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
5226 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
5227 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
5232 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
5233 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
5234 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
5235 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
5236 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
5237 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
5238 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
5239 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
5240 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5241 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5242 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
5243 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
5244 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
5245 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
5246 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5247 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5248 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5249 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5250 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5251 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
5299 NopInst.setOpcode(X86::NOOP);
5304 Branch.setOpcode(X86::JMP_4);
5309 MI.setOpcode(X86::TRAP);
5315 case X86::DIVSDrm:
5316 case X86::DIVSDrm_Int:
5317 case X86::DIVSDrr:
5318 case X86::DIVSDrr_Int:
5319 case X86::DIVSSrm:
5320 case X86::DIVSSrm_Int:
5321 case X86::DIVSSrr:
5322 case X86::DIVSSrr_Int:
5323 case X86::SQRTPDm:
5324 case X86::SQRTPDr:
5325 case X86::SQRTPSm:
5326 case X86::SQRTPSr:
5327 case X86::SQRTSDm:
5328 case X86::SQRTSDm_Int:
5329 case X86::SQRTSDr:
5330 case X86::SQRTSDr_Int:
5331 case X86::SQRTSSm:
5332 case X86::SQRTSSm_Int:
5333 case X86::SQRTSSr:
5334 case X86::SQRTSSr_Int:
5336 case X86::VDIVSDrm:
5337 case X86::VDIVSDrm_Int:
5338 case X86::VDIVSDrr:
5339 case X86::VDIVSDrr_Int:
5340 case X86::VDIVSSrm:
5341 case X86::VDIVSSrm_Int:
5342 case X86::VDIVSSrr:
5343 case X86::VDIVSSrr_Int:
5344 case X86::VSQRTPDm:
5345 case X86::VSQRTPDr:
5346 case X86::VSQRTPSm:
5347 case X86::VSQRTPSr:
5348 case X86::VSQRTSDm:
5349 case X86::VSQRTSDm_Int:
5350 case X86::VSQRTSDr:
5351 case X86::VSQRTSSm:
5352 case X86::VSQRTSSm_Int:
5353 case X86::VSQRTSSr:
5354 case X86::VSQRTPDZrm:
5355 case X86::VSQRTPDZrr:
5356 case X86::VSQRTPSZrm:
5357 case X86::VSQRTPSZrr:
5358 case X86::VSQRTSDZm:
5359 case X86::VSQRTSDZm_Int:
5360 case X86::VSQRTSDZr:
5361 case X86::VSQRTSSZm_Int:
5362 case X86::VSQRTSSZr:
5363 case X86::VSQRTSSZm:
5364 case X86::VDIVSDZrm:
5365 case X86::VDIVSDZrr:
5366 case X86::VDIVSSZrm:
5367 case X86::VDIVSSZrr:
5369 case X86::VGATHERQPSZrm:
5370 case X86::VGATHERQPDZrm:
5371 case X86::VGATHERDPDZrm:
5372 case X86::VGATHERDPSZrm:
5373 case X86::VPGATHERQDZrm:
5374 case X86::VPGATHERQQZrm:
5375 case X86::VPGATHERDDZrm:
5376 case X86::VPGATHERDQZrm:
5377 case X86::VSCATTERQPDZmr:
5378 case X86::VSCATTERQPSZmr:
5379 case X86::VSCATTERDPDZmr:
5380 case X86::VSCATTERDPSZmr:
5381 case X86::VPSCATTERQDZmr:
5382 case X86::VPSCATTERQQZmr:
5383 case X86::VPSCATTERDDZmr:
5384 case X86::VPSCATTERDQZmr:
5399 /// global base register for x86-32.
5433 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
5439 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
5445 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
5454 return "X86 PIC Global Base Reg Initialization";
5497 case X86::TLS_base_addr32:
5498 case X86::TLS_base_addr64:
5532 is64Bit ? X86::RAX : X86::EAX)
5553 ? &X86::GR64RegClass
5554 : &X86::GR32RegClass);
5561 .addReg(is64Bit ? X86::RAX : X86::EAX);
