Lines Matching refs:SHL
208 { ISD::SHL, MVT::v4i32, 1 },
211 { ISD::SHL, MVT::v8i32, 1 },
214 { ISD::SHL, MVT::v2i64, 1 },
216 { ISD::SHL, MVT::v4i64, 1 },
219 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
220 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
242 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
259 { ISD::SHL, MVT::v16i8, 1 }, // psllw.
260 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
261 { ISD::SHL, MVT::v4i32, 1 }, // pslld
262 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
290 if (ISD == ISD::SHL &&
314 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
315 { ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized.
316 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
317 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
318 { ISD::SHL, MVT::v4i64, 4*10 }, // Scalarized.
376 if (ISD == ISD::SHL && (VT == MVT::v8i32 || VT == MVT::v16i16) &&
1001 case Instruction::Shl:
