Lines Matching full:lsl
14 ; CHECK: sub sp, sp, #4095, lsl #12
15 ; CHECK: sub sp, sp, #4095, lsl #12
16 ; CHECK: sub sp, sp, #1575, lsl #12
21 ; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
22 ; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
29 ; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
30 ; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
42 ; CHECK: add sp, sp, #4095, lsl #12
43 ; CHECK: add sp, sp, #4095, lsl #12
44 ; CHECK: add sp, sp, #1575, lsl #12
55 ; CHECK: sub sp, sp, #488, lsl #12
59 ; CHECK: add [[VAR1ADDR:x[0-9]+]], sp, #244, lsl #12
62 ; CHECK: add [[VAR2ADDR:x[0-9]+]], sp, #244, lsl #12
66 ; CHECK: add sp, sp, #488, lsl #12
