Lines Matching full:mips
4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
5 ; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
7 ; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
9 ; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64
11 ; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64
21 %2 = tail call <16 x i8> @llvm.mips.insert.b(<16 x i8> %0, i32 1, i32 %1)
26 declare <16 x i8> @llvm.mips.insert.b(<16 x i8>, i32, i32) nounwind
28 ; MIPS-ANY: llvm_mips_insert_b_test:
29 ; MIPS-ANY-DAG: lw [[R1:\$[0-9]+]], 0(
30 ; MIPS-ANY-DAG: ld.b [[R2:\$w[0-9]+]], 0(
31 ; MIPS-ANY-DAG: insert.b [[R2]][1], [[R1]]
32 ; MIPS-ANY-DAG: st.b [[R2]], 0(
33 ; MIPS-ANY: .size llvm_mips_insert_b_test
43 %2 = tail call <8 x i16> @llvm.mips.insert.h(<8 x i16> %0, i32 1, i32 %1)
48 declare <8 x i16> @llvm.mips.insert.h(<8 x i16>, i32, i32) nounwind
50 ; MIPS-ANY: llvm_mips_insert_h_test:
51 ; MIPS-ANY-DAG: lw [[R1:\$[0-9]+]], 0(
52 ; MIPS-ANY-DAG: ld.h [[R2:\$w[0-9]+]], 0(
53 ; MIPS-ANY-DAG: insert.h [[R2]][1], [[R1]]
54 ; MIPS-ANY-DAG: st.h [[R2]], 0(
55 ; MIPS-ANY: .size llvm_mips_insert_h_test
65 %2 = tail call <4 x i32> @llvm.mips.insert.w(<4 x i32> %0, i32 1, i32 %1)
70 declare <4 x i32> @llvm.mips.insert.w(<4 x i32>, i32, i32) nounwind
72 ; MIPS-ANY: llvm_mips_insert_w_test:
73 ; MIPS-ANY-DAG: lw [[R1:\$[0-9]+]], 0(
74 ; MIPS-ANY-DAG: ld.w [[R2:\$w[0-9]+]], 0(
75 ; MIPS-ANY-DAG: insert.w [[R2]][1], [[R1]]
76 ; MIPS-ANY-DAG: st.w [[R2]], 0(
77 ; MIPS-ANY: .size llvm_mips_insert_w_test
87 %2 = tail call <2 x i64> @llvm.mips.insert.d(<2 x i64> %0, i32 1, i64 %1)
92 declare <2 x i64> @llvm.mips.insert.d(<2 x i64>, i32, i64) nounwind
94 ; MIPS-ANY: llvm_mips_insert_d_test:
105 ; MIPS-ANY: .size llvm_mips_insert_d_test
115 %2 = tail call <16 x i8> @llvm.mips.insve.b(<16 x i8> %0, i32 1, <16 x i8> %1)
120 declare <16 x i8> @llvm.mips.insve.b(<16 x i8>, i32, <16 x i8>) nounwind
122 ; MIPS-ANY: llvm_mips_insve_b_test:
127 ; MIPS-ANY-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])
128 ; MIPS-ANY-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])
129 ; MIPS-ANY-DAG: insve.b [[R3]][1], [[R4]][0]
130 ; MIPS-ANY-DAG: st.b [[R3]],
131 ; MIPS-ANY: .size llvm_mips_insve_b_test
141 %2 = tail call <8 x i16> @llvm.mips.insve.h(<8 x i16> %0, i32 1, <8 x i16> %1)
146 declare <8 x i16> @llvm.mips.insve.h(<8 x i16>, i32, <8 x i16>) nounwind
148 ; MIPS-ANY: llvm_mips_insve_h_test:
153 ; MIPS-ANY-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]])
154 ; MIPS-ANY-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]])
155 ; MIPS-ANY-DAG: insve.h [[R3]][1], [[R4]][0]
156 ; MIPS-ANY-DAG: st.h [[R3]],
157 ; MIPS-ANY: .size llvm_mips_insve_h_test
167 %2 = tail call <4 x i32> @llvm.mips.insve.w(<4 x i32> %0, i32 1, <4 x i32> %1)
172 declare <4 x i32> @llvm.mips.insve.w(<4 x i32>, i32, <4 x i32>) nounwind
174 ; MIPS-ANY: llvm_mips_insve_w_test:
179 ; MIPS-ANY-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]])
180 ; MIPS-ANY-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]])
181 ; MIPS-ANY-DAG: insve.w [[R3]][1], [[R4]][0]
182 ; MIPS-ANY-DAG: st.w [[R3]],
183 ; MIPS-ANY: .size llvm_mips_insve_w_test
193 %2 = tail call <2 x i64> @llvm.mips.insve.d(<2 x i64> %0, i32 1, <2 x i64> %1)
198 declare <2 x i64> @llvm.mips.insve.d(<2 x i64>, i32, <2 x i64>) nounwind
200 ; MIPS-ANY: llvm_mips_insve_d_test:
205 ; MIPS-ANY-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]])
206 ; MIPS-ANY-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]])
207 ; MIPS-ANY-DAG: insve.d [[R3]][1], [[R4]][0]
208 ; MIPS-ANY-DAG: st.d [[R3]],
209 ; MIPS-ANY: .size llvm_mips_insve_d_test
