Lines Matching full:lsl
27 ANDS r2, r2, r1, lsl #1 // Must use wide - shifted register
41 // CHECK: ands.w r2, r2, r1, lsl #1 @ encoding: [0x12,0xea,0x41,0x02]
69 ANDEQ r0, r0, r1, lsl #1 // Must use wide - shifted register
97 // CHECK: andeq.w r0, r0, r1, lsl #1 @ encoding: [0x00,0xea,0x41,0x00]
114 EORS r2, r2, r1, lsl #1 // Must use wide - shifted register
128 // CHECK: eors.w r2, r2, r1, lsl #1 @ encoding: [0x92,0xea,0x41,0x02]
156 EOREQ r4, r4, r1, lsl #1 // Must use wide - shifted register
184 // CHECK: eoreq.w r4, r4, r1, lsl #1 @ encoding: [0x84,0xea,0x41,0x04]
188 // LSL
194 LSL r4, r1, r4 // Must use wide encoding as not flag-setting
205 // CHECK: lsl.w r4, r1, r4 @ encoding: [0x01,0xfa,0x04,0xf4]
408 ADCS r3, r3, r1, lsl #1 // Must use wide - shifted register
422 // CHECK: adcs.w r3, r3, r1, lsl #1 @ encoding: [0x53,0xeb,0x41,0x03]
450 ADCEQ r2, r2, r1, lsl #1 // Must use wide - shifted register
478 // CHECK: adceq.w r2, r2, r1, lsl #1 @ encoding: [0x42,0xeb,0x41,0x02]
494 SBCS r2, r2, r1, lsl #1 // Must use wide - shifted register
507 // CHECK: sbcs.w r2, r2, r1, lsl #1 @ encoding: [0x72,0xeb,0x41,0x02]
533 SBCEQ r2, r2, r1, lsl #1 // Must use wide - shifted register
559 // CHECK: sbceq.w r2, r2, r1, lsl #1 @ encoding: [0x62,0xeb,0x41,0x02]
650 ORRS r1, r1, r1, lsl #1 // Must use wide - shifted register
664 // CHECK: orrs.w r1, r1, r1, lsl #1 @ encoding: [0x51,0xea,0x41,0x01]
692 ORREQ r2, r2, r1, lsl #1 // Must use wide - shifted register
720 // CHECK: orreq.w r2, r2, r1, lsl #1 @ encoding: [0x42,0xea,0x41,0x02]
738 BICS r3, r3, r1, lsl #1 // Must use wide - shifted register
751 // CHECK: bics.w r3, r3, r1, lsl #1 @ encoding: [0x33,0xea,0x41,0x03]
777 BICEQ r4, r4, r1, lsl #1 // Must use wide - shifted register
803 // CHECK: biceq.w r4, r4, r1, lsl #1 @ encoding: [0x24,0xea,0x41,0x04]
