Lines Matching refs:rc
167 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
170 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
171 const CodeGenRegister::Set &Regs = RC.getMembers();
176 RC.buildRegUnitSet(RegUnits);
180 OS << "}, \t// " << RC.getName() << "\n";
183 << " return RCWeightTable[RC->getID()];\n"
285 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
291 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
852 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
853 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
854 ArrayRef<Record*> Order = RC.getOrder();
857 std::string Name = RC.getName();
886 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
887 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
891 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
892 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
893 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
895 OS << " { " << '\"' << RC.getName() << "\", "
896 << RC.getName() << ", " << RC.getName() << "Bits, "
897 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
898 << RC.getQualifiedName() + "RegClassID" << ", "
899 << RC.SpillSize/8 << ", "
900 << RC
901 << RC.CopyCost << ", "
902 << RC.Allocatable << " },\n";
977 << "const TargetRegisterClass *RC) const override;\n"
983 << "const TargetRegisterClass *RC) const override;\n"
995 const CodeGenRegisterClass &RC = *RegisterClasses[i];
996 const std::string &Name = RC.getName();
1032 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1033 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1034 ArrayRef<Record*> Order = RC.getOrder();
1036 if (RC.Allocatable)
1042 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
1043 VTSeqs.add(RegisterClasses[rc]->VTs);
1074 // register class, RC, is the set of sub-classes, including RC itself.
1076 // If RC has super-registers, also create a list of subreg indices and bit
1080 // For all SuperReg in SuperRC: SuperReg:Idx in RC
1084 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
1097 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1098 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1099 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n ";
1100 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
1103 // project into RC.
1104 IdxList &SRIList = SuperRegIdxLists[rc];
1108 RC.getSuperRegClasses(Idx, MaskBV);
1126 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1127 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1128 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
1135 << RC.getName() << "Superclasses[] = {\n";
1143 const CodeGenRegisterClass &RC = *RegisterClasses[i];
1144 if (!RC.AltOrderSelect.empty()) {
1145 OS << "\nstatic inline unsigned " << RC.getName()
1147 << RC.AltOrderSelect << "}\n\n"
1148 << "static ArrayRef<MCPhysReg> " << RC.getName()
1150 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
1151 ArrayRef<Record*> Elems = RC.getOrder(oi);
1160 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
1163 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
1164 if (RC.getOrder(oi).empty())
1168 OS << ")\n };\n const unsigned Select = " << RC.getName()
1169 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
1179 const CodeGenRegisterClass &RC = *RegisterClasses[i];
1182 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
1184 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n "
1185 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + "
1187 if (RC.getSuperClasses().empty())
1190 OS << RC.getName() << "Superclasses,\n ";
1191 if (RC.AltOrderSelect.empty())
1194 OS << RC.getName() << "GetRawAllocationOrder\n";
1233 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1245 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
1246 OS << " {\t// " << RC.getName() << "\n";
1249 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
1257 OS << " };\n assert(RC && \"Missing regclass\");\n"
1258 << " if (!Idx) return RC;\n --Idx;\n"
1260 << " unsigned TV = Table[RC->getID()][Idx];\n"
