Lines Matching refs:rtex
61 unsigned r600_texture_get_offset(struct r600_texture *rtex,
64 return rtex->surface.level[level].offset +
65 layer * rtex->surface.level[level].slice_size;
161 struct r600_texture *rtex,
164 struct pipe_resource *ptex = &rtex->resource.b.b;
169 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
173 rtex->size = rtex->surface.bo_size;
174 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
178 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
179 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
180 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
181 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
182 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
186 switch (rtex->surface.level[i].mode) {
188 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
191 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
194 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
198 rtex->array_mode[i] = 0;
209 struct r600_texture *rtex = (struct r600_texture*)ptex;
210 struct r600_resource *resource = &rtex->resource;
211 struct radeon_surface *surface = &rtex->surface;
224 rtex->surface.level[0].pitch_bytes);
227 rtex->surface.level[0].pitch_bytes, whandle);
233 struct r600_texture *rtex = (struct r600_texture*)ptex;
234 struct r600_resource *resource = &rtex->resource;
236 if (rtex->flushed_depth_texture)
237 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
240 FREE(rtex);
257 struct r600_texture *rtex,
263 struct radeon_surface fmask = rtex->surface;
308 struct r600_texture *rtex)
312 r600_texture_get_fmask_info(rscreen, rtex,
313 rtex->resource.b.b.nr_samples, &fmask);
316 rtex->fmask_bank_height = fmask.bank_height;
317 rtex->fmask_offset = align(rtex->size, fmask.alignment);
318 rtex->fmask_size = fmask.size;
319 rtex->size = rtex->fmask_offset + rtex->fmask_size;
322 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
327 struct r600_texture *rtex,
344 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
345 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
356 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
360 struct r600_texture *rtex)
364 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
366 rtex->cmask_slice_tile_max = cmask.slice_tile_max;
367 rtex->cmask_offset = align(rtex->size, cmask.alignment);
368 rtex->cmask_size = cmask.size;
369 rtex->size = rtex->cmask_offset + rtex->cmask_size;
374 rtex->cmask_slice_tile_max);
386 struct r600_texture *rtex;
391 rtex = CALLOC_STRUCT(r600_texture);
392 if (rtex == NULL)
395 resource = &rtex->resource;
400 rtex->pitch_override = pitch_in_bytes_override;
403 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
405 rtex->surface = *surface;
406 r = r600_setup_surface(screen, rtex,
409 FREE(rtex);
413 if (base->nr_samples > 1 && !rtex->is_depth && alloc_bo) {
414 r600_texture_allocate_cmask(rscreen, rtex);
415 r600_texture_allocate_fmask(rscreen, rtex);
418 if (!rtex->is_depth && base->nr_samples > 1 &&
419 (!rtex->fmask_size || !rtex->cmask_size)) {
420 FREE(rtex);
426 unsigned base_align = rtex->surface.bo_alignment;
427 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
429 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, usage)) {
430 FREE(rtex);
439 if (rtex->cmask_size) {
442 memset(ptr + rtex->cmask_offset, 0xCC, rtex->cmask_size);
445 return rtex;
490 struct r600_texture *rtex = (struct r600_texture*)texture;
501 surface->base.width = rtex->surface.level[level].npix_x;
502 surface->base.height = rtex->surface.level[level].npix_y;
564 struct r600_texture *rtex = (struct r600_texture*)texture;
567 staging : &rtex->flushed_depth_texture;
569 if (!staging && rtex->flushed_depth_texture)
604 struct r600_texture *rtex = (struct r600_texture*)texture;
616 if (R600_TEX_IS_TILED(rtex, level)) {
622 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
623 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
642 if (rtex->is_depth) {
656 r600_blit_decompress_depth(ctx, rtex, staging_depth,
705 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
706 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
707 trans->offset = r600_texture_get_offset(rtex, level, box->z);
716 struct r600_texture *rtex = (struct r600_texture*)texture;
719 if (rtex->is_depth) {
742 struct r600_texture *rtex =
758 if (rtex->is_depth || !rtransfer->staging)
