Lines Matching refs:vec4_instruction
147 class vec4_instruction : public exec_node {
161 vec4_instruction(vec4_visitor *v, enum opcode opcode,
332 vec4_instruction *emit(vec4_instruction *inst);
334 vec4_instruction *emit(enum opcode opcode);
336 vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
338 vec4_instruction *emit(enum opcode opcode, dst_reg dst,
341 vec4_instruction *emit(enum opcode opcode, dst_reg dst,
344 vec4_instruction *emit_before(vec4_instruction *inst,
345 vec4_instruction *new_inst);
347 vec4_instruction *MOV(dst_reg dst, src_reg src0);
348 vec4_instruction *NOT(dst_reg dst, src_reg src0);
349 vec4_instruction *RNDD(dst_reg dst, src_reg src0);
350 vec4_instruction *RNDE(dst_reg dst, src_reg src0);
351 vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
352 vec4_instruction *FRC(dst_reg dst, src_reg src0);
353 vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
354 vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
355 vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
356 vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
357 vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
358 vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
359 vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
360 vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
361 vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
362 vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
364 vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
365 vec4_instruction *IF(uint32_t predicate);
366 vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
367 vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
368 vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
370 int implied_mrf_writes(vec4_instruction *inst);
375 vec4_instruction *pre_rhs_inst,
376 vec4_instruction *last_rhs_inst);
420 src_reg get_scratch_offset(vec4_instruction *inst,
422 src_reg get_pull_constant_offset(vec4_instruction *inst,
424 void emit_scratch_read(vec4_instruction *inst,
428 void emit_scratch_write(vec4_instruction *inst,
432 void emit_pull_constant_load(vec4_instruction *inst,
443 void generate_vs_instruction(vec4_instruction *inst,
447 void generate_math1_gen4(vec4_instruction *inst,
450 void generate_math1_gen6(vec4_instruction *inst,
453 void generate_math2_gen4(vec4_instruction *inst,
457 void generate_math2_gen6(vec4_instruction *inst,
461 void generate_math2_gen7(vec4_instruction *inst,
466 void generate_tex(vec4_instruction *inst,
470 void generate_urb_write(vec4_instruction *inst);
473 void generate_scratch_write(vec4_instruction *inst,
477 void generate_scratch_read(vec4_instruction *inst,
480 void generate_pull_constant_load(vec4_instruction *inst,
