Lines Matching refs:t6
17 register uint32_t t0, t1, t2, t3, t4, t5, t6;
48 "shrl.qb %[t6], %[t0], 3 \n\t"
57 "subu.qb %[t6], %[t6], %[t3] \n\t"
60 "muleu_s.ph.qbr %[t6], %[s4], %[t6] \n\t"
65 "shra.ph %[t6], %[t6], 8 \n\t"
68 "addu.qb %[t6], %[t6], %[t3] \n\t"
73 "sll %[t0], %[t6], 0xb \n\t"
80 "srl %[s0], %[t6], 16 \n\t"
88 [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6), [s0]"=&r"(s0),
121 register int32_t t0, t1, t2, t3, t4, t5, t6;
147 "srav %[t6], %[dither_scan], %[t5] \n\t"
149 "ins %[t3], %[t6], 8, 4 \n\t"
160 "subu.qb %[t6], %[t3], %[t5] \n\t"
161 "addq.ph %[t5], %[t6], %[t4] \n\t"
163 "srl %[t6], %[t2], 8 \n\t"
164 "ins %[t4], %[t6], 16, 8 \n\t"
165 "shrl.qb %[t6], %[t4], 6 \n\t"
167 "subu.qb %[t8], %[t7], %[t6] \n\t"
168 "addq.ph %[t6], %[t8], %[t4] \n\t"
178 "andi %[t3], %[t6], 0xffff \n\t"
179 "srl %[t4], %[t6], 16 \n\t"
180 "andi %[t6], %[t5], 0xffff \n\t"
186 "sll %[t1], %[t6], 13 \n\t"
191 "sll %[t6], %[t3], 0x10 \n\t"
193 "or %[t5], %[t6], %[t8] \n\t"
194 "andi %[t6], %[t0], 0xff \n\t"
195 "mul %[t1], %[t6], %[t5] \n\t"
197 "srl %[t6], %[t5], 5 \n\t"
198 "and %[t5], %[s2], %[t6] \n\t"
199 "srl %[t8], %[t6], 16 \n\t"
200 "andi %[t6], %[t8], 0x7e0 \n\t"
201 "or %[t1], %[t5], %[t6] \n\t"
211 "sll %[t6], %[t3], 0x10 \n\t"
213 "or %[t5], %[t6], %[t8] \n\t"
214 "srl %[t6], %[t0], 16 \n\t"
215 "mul %[t1], %[t6], %[t5] \n\t"
217 "srl %[t6], %[t5], 5 \n\t"
218 "and %[t5], %[s2], %[t6] \n\t"
219 "srl %[t8], %[t6], 16 \n\t"
220 "andi %[t6], %[t8], 0x7e0 \n\t"
221 "or %[t1], %[t5], %[t6] \n\t"
232 [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6), [t7]"=&r"(t7),
270 register uint32_t t6, t7, t8, t9, s0;
311 "sll %[t6], %[t0], 16 \n\t"
313 "precrq.ph.w %[t8], %[t6], %[t7] \n\t"
320 "shra.ph %[t6], %[t3], 3 \n\t"
330 "precrq.ph.w %[t0], %[t6], %[t7] \n\t"
332 "append %[t6], %[t7], 16 \n\t"
334 "sll %[t6], %[t6], 16 \n\t"
336 "precrq.ph.w %[t6], %[t6], %[t2] \n\t"
346 "sra %[t8], %[t6], 5 \n\t"
348 "or %[t3], %[t9], %[t6] \n\t"
360 [t3]"=&r"(t3), [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6),
378 register int32_t t0, t1, t2, t3, t4, t5, t6;
437 "sll %[t6], %[s1], 8 \n\t"
438 "precrq.qb.ph %[t4], %[t5], %[t6] \n\t"
439 "precrq.qb.ph %[t6], %[s0], %[s1] \n\t"
442 "preceu.ph.qbra %[t6], %[t6] \n\t"
464 "shrl.qb %[t3], %[t6], 6 \n\t"
465 "addu.qb %[t6], %[t6], %[t1] \n\t"
466 "subu.qb %[t6], %[t6], %[t3] \n\t"
467 "shrl.qb %[t6], %[t6], 2 \n\t"
484 "cmpu.lt.qb %[t6], %[s2] \n\t"
487 "subu.qb %[t6], %[t6], %[s2] \n\t"
488 "muleu_s.ph.qbl %[t0], %[t6], %[sc_mul] \n\t"
489 "muleu_s.ph.qbr %[t1], %[t6], %[sc_mul] \n\t"
490 "precrq.qb.ph %[t6], %[t0], %[t1] \n\t"
491 "addu.qb %[t6], %[t6], %[s0] \n\t"
493 "shll.ph %[t0], %[t6], 5 \n\t"
509 [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6), [s0]"=&r"(s0),
550 register uint32_t t0, t1, t2, t3, t4, t5, t6, t7, t8;
582 "sll %[t6], %[t1], 16 \n\t"
583 "precrq.ph.w %[t0], %[t0], %[t6] \n\t"
602 "shra.ph %[t6], %[t0], 11 \n\t"
603 "and %[t6], %[t6], 0x1f001f \n\t"
606 "muleu_s.ph.qbl %[t0], %[t2], %[t6] \n\t"
608 "shra.ph %[t6], %[t7], 5 \n\t"
609 "addq.ph %[t6], %[t7], %[t6
610 "shra.ph %[t0], %[t6], 5 \n\t"
612 "shra.ph %[t6], %[t7], 3 \n\t"
628 "shll.ph %[t1], %[t6], 11 \n\t"
642 [t3]"=&r"(t3), [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6),
661 register uint32_t t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
669 "repl.ph %[t6], 0x80 \n\t"
695 "addq.ph %[s3], %[s3], %[t6] \n\t"
715 "addq.ph %[t8], %[t1], %[t6] \n\t"
716 "addq.ph %[t9], %[t2], %[t6] \n\t"
717 "addq.ph %[t4], %[t3], %[t6] \n\t"
745 [t6]"=&r"(t6), [t7]"=&r"(t7), [t8]"=&r"(t8), [t9]"=&r"(t9)
771 register int32_t t0, t1, t2, t3, t4, t5, t6, t7;
780 "replv.qb %[t6], %[t1] \n\t"
791 "muleu_s.ph.qbr %[t4], %[t6], %[t4] \n\t"
792 "muleu_s.ph.qbr %[t5], %[t6], %[t5] \n\t"
805 [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6), [t7]"=&r"(t7)
