Lines Matching refs:ULL
309 #define AMD64G_CC_MASK_O (1ULL << AMD64G_CC_SHIFT_O)
310 #define AMD64G_CC_MASK_S (1ULL << AMD64G_CC_SHIFT_S)
311 #define AMD64G_CC_MASK_Z (1ULL << AMD64G_CC_SHIFT_Z)
312 #define AMD64G_CC_MASK_A (1ULL << AMD64G_CC_SHIFT_A)
313 #define AMD64G_CC_MASK_C (1ULL << AMD64G_CC_SHIFT_C)
314 #define AMD64G_CC_MASK_P (1ULL << AMD64G_CC_SHIFT_P)
322 #define AMD64G_FC_MASK_C3 (1ULL << AMD64G_FC_SHIFT_C3)
323 #define AMD64G_FC_MASK_C2 (1ULL << AMD64G_FC_SHIFT_C2)
324 #define AMD64G_FC_MASK_C1 (1ULL << AMD64G_FC_SHIFT_C1)
325 #define AMD64G_FC_MASK_C0 (1ULL << AMD64G_FC_SHIFT_C0)
