Lines Matching refs:rD
70 - pretty dodgy exception semantics for {LD,ST}Mxx and {LD,ST}RD.
2616 Also produce the t/e chars for the 2nd, 3rd, 4th insns, for
7829 void mk_neon_elem_load_to_one_lane( UInt rD, UInt inc, UInt index,
7835 putDRegI64(rD, triop(Iop_SetElem8x8, getDRegI64(rD), mkU8(index),
7839 putDRegI64(rD, triop(Iop_SetElem16x4, getDRegI64(rD), mkU8(index),
7843 putDRegI64(rD, triop(Iop_SetElem32x2, getDRegI64(rD), mkU8(index),
7852 putDRegI64(rD + i * inc,
7854 getDRegI64(rD + i * inc),
7862 putDRegI64(rD + i * inc,
7864 getDRegI64(rD + i * inc),
7872 putDRegI64(rD + i * inc,
7874 getDRegI64(rD + i * inc),
7890 void mk_neon_elem_store_from_one_lane( UInt rD, UInt inc, UInt index,
7897 binop(Iop_GetElem8x8, getDRegI64(rD), mkU8(index)));
7901 binop(Iop_GetElem16x4, getDRegI64(rD), mkU8(index)));
7905 binop(Iop_GetElem32x2, getDRegI64(rD), mkU8(index)));
7914 binop(Iop_GetElem8x8, getDRegI64(rD + i * inc),
7919 binop(Iop_GetElem16x4, getDRegI64(rD + i * inc),
7924 binop(Iop_GetElem32x2, getDRegI64(rD + i * inc),
8331 UInt rD = (INSN(22,22) << 4) | INSN(15,12);
8385 mk_neon_elem_load_to_one_lane(rD, inc, i, N, size, addr);
8387 mk_neon_elem_store_from_one_lane(rD, inc, i, N, size, addr);
8392 DIP("d%u[%u]", rD + j * inc, i);
8435 putDRegI64(rD + r, unop(Iop_Dup8x8,
8440 putDRegI64(rD + r, unop(Iop_Dup16x4,
8445 putDRegI64(rD + r, unop(Iop_Dup32x2,
8455 putDRegI64(rD + r + i * inc,
8463 putDRegI64(rD + r + i * inc,
8471 putDRegI64(rD + r + i * inc,
8488 DIP("d%u[]", rD + r + i * inc);
8531 if (rD + regs > 32) return False;
8538 if (regs == 1 && inc == 1 && rD + 1 >= 32) return False;
8539 if (regs == 1 && inc == 2 && rD + 2 >= 32) return False;
8540 if (regs == 2 && inc == 2 && rD + 3 >= 32) return False;
8543 if (inc == 1 && rD + 2 >= 32) return False;
8544 if (inc == 2 && rD + 4 >= 32) return False;
8547 if (inc == 1 && rD + 3 >= 32) return False;
8548 if (inc == 2 && rD + 6 >= 32) return False;
8585 putDRegI64(rD+r, loadLE(Ity_I64, mkexpr(addr)), IRTemp_INVALID);
8587 storeLE(mkexpr(addr), getDRegI64(rD+r));
8627 putDRegI64(rD + 0 * regstep, mkexpr(du0), IRTemp_INVALID);
8628 putDRegI64(rD + 1 * regstep, mkexpr(du1), IRTemp_INVALID);
8630 assign(du0, getDRegI64(rD + 0 * regstep));
8631 assign(du1, getDRegI64(rD + 1 * regstep));
8662 putDRegI64(rD + 0 * regstep, mkexpr(du0), IRTemp_INVALID);
8663 putDRegI64(rD + 1 * regstep, mkexpr(du1), IRTemp_INVALID);
8664 putDRegI64(rD + 2 * regstep, mkexpr(du2), IRTemp_INVALID);
8665 putDRegI64(rD + 3 * regstep, mkexpr(du3), IRTemp_INVALID);
8667 assign(du0, getDRegI64(rD + 0 * regstep));
8668 assign(du1, getDRegI64(rD + 1 * regstep));
8669 assign(du2, getDRegI64(rD + 2 * regstep));
8670 assign(du3, getDRegI64(rD + 3 * regstep));
8704 putDRegI64(rD + 0 * inc, mkexpr(du0), IRTemp_INVALID);
8705 putDRegI64(rD + 1 * inc, mkexpr(du1), IRTemp_INVALID);
8706 putDRegI64(rD + 2 * inc, mkexpr(du2), IRTemp_INVALID);
8708 assign(du0, getDRegI64(rD + 0 * inc));
8709 assign(du1, getDRegI64(rD + 1 * inc));
8710 assign(du2, getDRegI64(rD + 2 * inc));
8744 putDRegI64(rD + 0 * inc, mkexpr(du0), IRTemp_INVALID);
8745 putDRegI64(rD + 1 * inc, mkexpr(du1), IRTemp_INVALID);
8746 putDRegI64(rD + 2 * inc, mkexpr(du2), IRTemp_INVALID);
8747 putDRegI64(rD + 3 * inc, mkexpr(du3), IRTemp_INVALID);
8749 assign(du0, getDRegI64(rD + 0 * inc));
8750 assign(du1, getDRegI64(rD + 1 * inc));
8751 assign(du2, getDRegI64(rD + 2 * inc));
8752 assign(du3, getDRegI64(rD + 3 * inc));
8787 DIP("d%u-d%u", rD, rD + regs * (N + 1) - 1);
8794 DIP("d%u", rD + r + i * inc);
9000 /* ------------ smulwb<y><c> <Rd>,<Rn>,<Rm> ------------- */
9001 /* ------------ smulwt<y><c> <Rd>,<Rn>,<Rm> ------------- */
9061 /* ------------ pkhbt<c> Rd, Rn, Rm {,LSL #imm} ------------- */
9062 /* ------------ pkhtb<c> Rd, Rn, Rm {,ASR #imm} ------------- */
9122 /* ---------- usat<c> <Rd>,#<imm5>,<Rn>{,<shift>} ----------- */
9180 /* ----------- ssat<c> <Rd>,#<imm5>,<Rn>{,<shift>} ----------- */
9238 /* ----------- ssat16<c> <Rd>,#<imm>,<Rn> ----------- */
9302 /* -------------- usat16<c> <Rd>,#<imm4>,<Rn> --------------- */
9363 /* -------------- uadd16<c> <Rd>,<Rn>,<Rm> -------------- */
9412 /* -------------- sadd16<c> <Rd>,<Rn>,<Rm> -------------- */
9462 /* ---------------- usub16<c> <Rd>,<Rn>,<Rm> ---------------- */
9512 /* -------------- ssub16<c> <Rd>,<Rn>,<Rm> -------------- */
9562 /* ----------------- uadd8<c> <Rd>,<Rn>,<Rm> ---------------- */
9611 /* ------------------- sadd8<c> <Rd>,<Rn>,<Rm> ------------------ */
9661 /* ------------------- usub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9711 /* ------------------- ssub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9761 /* ------------------ qadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9806 /* ------------------ qsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
9851 /* ------------------ uqadd8<c> <Rd>,<Rn>,<Rm> ------------------ */
9896 /* ------------------ uqsub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9941 /* ----------------- uhadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9986 /* ----------------- uhadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
10031 /* ----------------- shadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
10076 /* ------------------ qadd16<c> <Rd>,<Rn>,<Rm> ------------------ */
10121 /* ------------------ qsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
10166 /* ------------------- qsax<c> <Rd>,<Rn>,<Rm> ------------------- */
10237 /* ------------------- qasx<c> <Rd>,<Rn>,<Rm> ------------------- */
10305 /* ------------------- sasx<c> <Rd>,<Rn>,<Rm> ------------------- */
10379 /* --------------- smuad, smuadx<c><Rd>,<Rn>,<Rm> --------------- */
10380 /* --------------- smsad, smsadx<c><Rd>,<Rn>,<Rm> --------------- */
10458 /* --------------- smlad{X}<c> <Rd>,<Rn>,<Rm>,<Ra> -------------- */
10459 /* --------------- smlsd{X}<c> <Rd>,<Rn>,<Rm>,<Ra> -------------- */
10549 /* ----- smlabb, smlabt, smlatb, smlatt <Rd>,<Rn>,<Rm>,<Ra> ----- */
10619 /* ----- smlalbb, smlalbt, smlaltb, smlaltt <Rd>,<Rn>,<Rm>,<Ra> ----- */
10694 /* ----- smlawb, smlawt <Rd>,<Rn>,<Rm>,<Ra> ----- */
10765 /* ------------------- sel<c> <Rd>,<Rn>,<Rm> -------------------- */
10853 /* ----------------- uxtab16<c> Rd,Rn,Rm{,rot} ------------------ */
10916 /* --------------- usad8 Rd,Rn,Rm ---------------- */
10917 /* --------------- usada8 Rd,Rn,Rm,Ra ---------------- */
10919 UInt rD = 99, rN = 99, rM = 99, rA = 99;
10926 rD = INSNT1(11,8);
10928 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && rA != 13)
10934 rD = INSNA(19,16);
10938 if (rD != 15 && rN != 15 && rM != 15 /* but rA can be 15 */)
10953 putIRegT( rD, res, condT );
10955 putIRegA( rD, res, condT, Ijk_Boring );
10959 nCC(conq), rD, rN, rM );
10962 nCC(conq), rD, rN, rM, rA );
10969 /* ------------------ qadd<c> <Rd>,<Rn>,<Rm> ------------------- */
11020 /* ------------------ qdadd<c> <Rd>,<Rm>,<Rn> ------------------- */
11079 /* ------------------ qsub<c> <Rd>,<Rn>,<Rm> ------------------- */
11130 /* ------------------ qdsub<c> <Rd>,<Rm>,<Rn> ------------------- */
11189 /* ------------------ uqsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
11234 /* ----------------- shadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
11279 /* ----------------- uhsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
11324 /* ----------------- uhsub16<c> <Rd>,<Rn>,<Rm> ------------------- */
11369 /* ------------------ uqadd16<c> <Rd>,<Rn>,<Rm> ------------------ */
11414 /* ------------------- uqsax<c> <Rd>,<Rn>,<Rm> ------------------- */
11483 /* ------------------- uqasx<c> <Rd>,<Rn>,<Rm> ------------------- */
11551 /* ------------------- usax<c> <Rd>,<Rn>,<Rm> ------------------- */
11629 /* ------------------- uasx<c> <Rd>,<Rn>,<Rm> ------------------- */
11705 /* ------------------- ssax<c> <Rd>,<Rn>,<Rm> ------------------- */
11779 /* ----------------- shsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
11824 /* ----------------- sxtab16<c> Rd,Rn,Rm{,rot} ------------------ */
11899 /* ----------------- shasx<c> <Rd>,<Rn>,<Rm> ------------------- */
11996 /* ----------------- uhasx<c> <Rd>,<Rn>,<Rm> ------------------- */
12093 /* ----------------- shsax<c> <Rd>,<Rn>,<Rm> ------------------- */
12190 /* ----------------- uhsax<c> <Rd>,<Rn>,<Rm> ------------------- */
12287 /* ----------------- shsub16<c> <Rd>,<Rn>,<Rm> ------------------- */
12332 /* ----------------- smmls{r}<c> <Rd>,<Rn>,<Rm>,<Ra> ------------------- */
12334 UInt rD = 99, rN = 99, rM = 99, rA = 99;
12344 rD = INSNT1(11,8);
12347 if (!isBadRegT(rD)
12356 rD = INSNA(19,16);
12360 if (rD != 15 && rM != 15 && rN != 15)
12379 putIRegT( rD, res, condT );
12381 putIRegA(rD, res, condT, Ijk_Boring);
12383 round ? "r" : "", nCC(conq), rD, rN, rM, rA);
13104 UInt rD = INSN(15,12);
13107 if (rD == 15) {
13109 /* When rD is 15, we are copying the top 4 bits of FPSCR
13121 putIRegT(rD, e, condT);
13123 putIRegA(rD, e, condT, Ijk_Boring);
13124 DIP("fmrx%s r%u, fpscr\n", nCC(conq), rD);
13134 UInt rD = INSN(15,12);
13138 isT ? getIRegT(rD) : getIRegA(rD), condT);
13139 DIP("fmxr%s fpscr, r%u\n", nCC(conq), rD);
13146 // VMOV dM, rD, rN
13149 UInt rD = INSN(15,12); /* lo32 */
13151 if (rD == 15 || rN == 15 || (isT && (rD == 13 || rN == 13))) {
13158 isT ? getIRegT(rD) : getIRegA(rD))),
13160 DIP("vmov%s d%u, r%u, r%u\n", nCC(conq), dM, rD, rN);
13166 // VMOV rD, rN, dM
13169 UInt rD = INSN(15,12); /* lo32 */
13171 if (rD == 15 || rN == 15 || (isT && (rD == 13 || rN == 13))
13172 || rD == rN) {
13181 putIRegT(rD, lo32, condT);
13184 putIRegA(rD, lo32, condT, Ijk_Boring);
13186 DIP("vmov%s r%u, r%u, d%u\n", nCC(conq), rD, rN, dM);
13237 // VMOV rD[x], rT (ARM core register to scalar)
13239 UInt rD = (INSN(7,7) << 4) | INSN(19,16);
13248 putDRegI64(rD, triop(Iop_SetElem8x8,
13249 getDRegI64(rD),
13254 DIP("vmov%s.8 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
13259 putDRegI64(rD, triop(Iop_SetElem16x4,
13260 getDRegI64(rD),
13265 DIP("vmov%s.16 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
13270 putDRegI64(rD, triop(Iop_SetElem32x2,
13271 getDRegI64(rD),
13275 DIP("vmov%s.32 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
13284 // VMOV rT, rD[x]
13341 UInt rD = (INSN(15,12) << 1) | INSN(22,22);
13348 putFReg(rD, unop(Iop_ReinterpI32asF32, mkU32(imm)), condT);
13349 DIP("fconsts%s s%u #%u", nCC(conq), rD, imm8);
13357 UInt rD = INSN(15,12) | (INSN(22,22) << 4);
13364 putDReg(rD, unop(Iop_ReinterpI64asF64, mkU64(imm)), condT);
13365 DIP("fconstd%s d%u #%u", nCC(conq), rD, imm8);
13374 UInt rD = (INSN(7,7) << 4) | INSN(19,16);
13378 if (rT == 15 || (isT && rT == 13) || size == 3 || (Q && (rD & 1))) {
13383 rD >>= 1;
13386 putQReg(rD, unop(Iop_Dup32x4, e), condT);
13389 putQReg(rD, unop(Iop_Dup16x8, unop(Iop_32to16, e)),
13393 putQReg(rD, unop(Iop_Dup8x16, unop(Iop_32to8, e)),
13399 DIP("vdup.%u q%u, r%u\n", 32 / (1<<size), rD, rT);
13403 putDRegI64(rD, unop(Iop_Dup32x2, e), condT);
13406 putDRegI64(rD, unop(Iop_Dup16x4, unop(Iop_32to16, e)),
13410 putDRegI64(rD, unop(Iop_Dup8x8, unop(Iop_32to8, e)),
13416 DIP("vdup.%u d%u, r%u\n", 32 / (1<<size), rD, rT);
13875 UInt rD = INSN(15,12);
13879 if (rD == 15) {
13889 putIRegT(rD, res, condT);
13891 putIRegA(rD, res, condT, Ijk_Boring);
13892 DIP("fmrs%s r%u, s%u\n", nCC(conq), rD, fN);
13895 isT ? getIRegT(rD) : getIRegA(rD)),
13897 DIP("fmsr%s s%u, r%u\n", nCC(conq), fN, rD);
14708 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
14722 case BITS4(0,1,0,0): /* ADD: Rd = Rn + shifter_operand */
14724 case BITS4(0,0,1,0): /* SUB: Rd = Rn - shifter_operand */
14726 case BITS4(0,0,1,1): /* RSB: Rd = shifter_operand - Rn */
14728 case BITS4(0,0,0,0): /* AND: Rd = Rn & shifter_operand */
14730 case BITS4(1,1,0,0): /* OR: Rd = Rn | shifter_operand */
14732 case BITS4(0,0,0,1): /* EOR: Rd = Rn ^ shifter_operand */
14734 case BITS4(1,1,1,0): /* BIC: Rd = Rn & ~shifter_operand */
14779 putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
14810 name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
14815 case BITS4(1,1,0,1): /* MOV: Rd = shifter_operand */
14816 case BITS4(1,1,1,1): { /* MVN: Rd = not(shifter_operand) */
14843 putIRegA( rD, mkexpr(res), condT, jk );
14851 nCC(INSN_COND), bitS ? "s" : "", rD, dis_buf );
14859 if (rD != 0)
14860 break; /* rD must be zero */
14885 if (rD != 0)
14886 break; /* rD must be zero */
14913 case BITS4(0,1,0,1): /* ADC: Rd = Rn + shifter_operand + oldC */
14915 case BITS4(0,1,1,0): /* SBC: Rd = Rn - shifter_operand - (oldC ^ 1) */
14917 case BITS4(0,1,1,1): /* RSC: Rd = shifter_operand - Rn - (oldC ^ 1) */
14958 putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
14984 name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
14997 A5-20 1 | 16 cond 0101 UB0L Rn Rd imm12
14998 A5-22 1 | 32 cond 0111 UBOL Rn Rd imm5 sh2 0 Rm
14999 A5-24 2 | 16 cond 0101 UB1L Rn Rd imm12
15000 A5-26 2 | 32 cond 0111 UB1L Rn Rd imm5 sh2 0 Rm
15001 A5-28 3 | 16 cond 0100 UB0L Rn Rd imm12
15002 A5-32 3 | 32 cond 0110 UB0L Rn Rd imm5 sh2 0 Rm
15042 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
15062 if (bL == 1 && rN == rD) goto after_load_store_ubyte_or_word;
15068 if (bL == 1 && rN == rD) goto after_load_store_ubyte_or_word;
15114 assign(rDt, getIRegA(rD));
15149 mkexpr(taT), llGetIReg(rD), condT );
15150 /* "rD == 15 ? condT : IRTemp_INVALID": simply
15159 putIRegA( rD, mkexpr(tD),
15160 rD == 15 ? condT : IRTemp_INVALID, jk );
15164 loadGuardedLE( tD, ILGop_8Uto32, mkexpr(taT), llGetIReg(rD), condT );
15165 /* No point in similar 3rd arg complexity here, since we
15167 putIRegA( rD, mkexpr(tD), IRTemp_INVALID, Ijk_Boring );
15175 vassert(rD != rN); /* since we just wrote rD */
15184 bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
15188 bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
15192 bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
15204 writeback, and the same register is specified for Rd and Rn,
15224 A5-36 1 | 16 cond 0001 U10L Rn Rd im4h 1SH1 im4l
15225 A5-38 1 | 32 cond 0001 U00L Rn Rd 0000 1SH1 Rm
15226 A5-40 2 | 16 cond 0001 U11L Rn Rd im4h 1SH1 im4l
15227 A5-42 2 | 32 cond 0001 U01L Rn Rd 0000 1SH1 Rm
15228 A5-44 3 | 16 cond 0000 U10L Rn Rd im4h 1SH1 im4l
15229 A5-46 3 | 32 cond 0000 U00L Rn Rd 0000 1SH1 Rm
15270 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
15301 if (bL == 1 && rN == rD) goto after_load_store_sbyte_or_hword;
15307 if (bL == 1 && rN == rD) goto after_load_store_sbyte_or_hword;
15318 if (bL == 1 && rD == 15 && condT != IRTemp_INVALID) {
15352 /* ll previous value of rD, for dealing with conditional loads */
15354 assign(llOldRd, llGetIReg(rD));
15365 unop(Iop_32to16, getIRegA(rD)), condT );
15372 putIRegA( rD, mkexpr(newRd), IRTemp_INVALID, Ijk_Boring );
15379 putIRegA( rD, mkexpr(newRd), IRTemp_INVALID, Ijk_Boring );
15386 putIRegA( rD, mkexpr(newRd), IRTemp_INVALID, Ijk_Boring );
15397 vassert(rD != rN); /* since we just wrote rD */
15403 case 1: DIP("%s%s r%u, %s\n", name, nCC(INSN_COND), rD, dis_buf);
15406 name, nCC(INSN_COND), rD, dis_buf);
15409 name, nCC(INSN_COND), rD, dis_buf);
15421 writeback, and the same register is specified for Rd and Rn,
15626 UInt rD = INSN(15,12);
15636 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
15637 DIP("clz%s r%u, r%u\n", nCC(INSN_COND), rD, rM);
15647 UInt rD = INSN(19,16);
15650 if (rD == 15 || rM == 15 || rS == 15) {
15668 putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
15677 bitS ? 's' : ' ', nCC(INSN_COND), rD, rM, rS);
15688 UInt rD = INSN(19,16);
15691 if (rD == 15 || rM == 15 || rN == 15) {
15700 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
15701 DIP("sdiv r%u, r%u, r%u\n", rD, rN, rM);
15710 UInt rD = INSN(19,16);
15713 if (rD == 15 || rM == 15 || rN == 15) {
15722 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
15723 DIP("udiv r%u, r%u, r%u\n", rD, rN, rM);
15733 UInt rD = INSN(19,16);
15742 if (rD == 15 || rM == 15 || rS == 15 || rN == 15) {
15765 putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
15775 nCC(INSN_COND), rD, rM, rS, rN);
15961 // MRS rD, cpsr
15963 UInt rD = INSN(15,12);
15964 if (rD != 15) {
15966 putIRegA( rD, mkexpr(apsr), condT, Ijk_Boring );
15967 DIP("mrs%s r%u, cpsr\n", nCC(INSN_COND), rD);
15998 UInt rD = INSN(15,12);
16006 if (rD == 15 || rN == 15 || rM == 15 || rN == rM || rN == rD) {
16036 putIRegA(rD, isB ? unop(Iop_8Uto32, mkexpr(tOld)) : mkexpr(tOld),
16039 isB ? "b" : "", nCC(INSN_COND), rD, rM, rN);
16109 UInt rD = INSN(15,12);
16122 if (rD == 15 || rN == 15 || rT == 15
16123 || rD == rN || rD == rT)
16127 if (rD == 15 || (rT & 1) == 1 || rT == 14 || rN == 15
16128 || rD == rN || rD == rT || rD == rT+1)
16151 /* Set rD to 1 on failure, 0 on success. Currently we have
16157 putIRegA(rD, mkexpr(resSC32),
16161 nm, nCC(INSN_COND), rD, rT, rT+1, rN);
16164 nm, nCC(INSN_COND), rD, rT, rN);
16174 UInt rD = INSN(15,12);
16177 if (rD == 15) {
16181 putIRegA(rD,
16183 binop(Iop_And32, getIRegA(rD), mkU32(0xFFFF)),
16186 DIP("movt%s r%u, #0x%04x\n", nCC(INSN_COND), rD, imm16);
16189 putIRegA(rD, mkU32(imm16), condT, Ijk_Boring);
16190 DIP("movw%s r%u, #0x%04x\n", nCC(INSN_COND), rD, imm16);
16208 UInt rD = INSN(15,12);
16259 putIRegA(rD, mkexpr(dstT), condT, Ijk_Boring);
16260 DIP("%s%s r%u, r%u, ROR #%u\n", nm, nCC(INSN_COND), rD, rM, rot);
16269 UInt rD = INSN(15,12);
16273 if (rD == 15 || msb < lsb) {
16285 assign(olddst, getIRegA(rD));
16296 putIRegA(rD, mkexpr(newdst), condT, Ijk_Boring);
16300 nCC(INSN_COND), rD, lsb, msb-lsb+1);
16303 nCC(INSN_COND), rD, rN, lsb, msb-lsb+1);
16313 UInt rD = INSN(15,12);
16319 if (rD == 15 || rN == 15 || msb >= 32) {
16337 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
16341 nCC(INSN_COND), rD, rN, lsb, wm1 + 1);
16351 A5-36 1 | 16 cond 0001 U100 Rn Rd im4h 11S1 im4l
16352 A5-38 1 | 32 cond 0001 U000 Rn Rd 0000 11S1 Rm
16353 A5-40 2 | 16 cond 0001 U110 Rn Rd im4h 11S1 im4l
16354 A5-42 2 | 32 cond 0001 U010 Rn Rd 0000 11S1 Rm
16355 A5-44 3 | 16 cond 0000 U100 Rn Rd im4h 11S1 im4l
16356 A5-46 3 | 32 cond 0000 U000 Rn Rd 0000 11S1 Rm
16397 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
16403 /* Require rD to be an even numbered register */
16404 if ((rD & 1) != 0)
16422 if (bS == 0 && (rN == rD || rN == rD+1))
16429 if (bS == 0 && (rN == rD || rN == rD+1))
16439 vassert((rD & 1) == 0); /* from tests above */
16440 if (bS == 0 && rD+1 == 15 && condT != IRTemp_INVALID) {
16480 strd rD, [sp, #-8]
16486 && rN == 13 && rN != rD && rN != rD+1
16499 getIRegA(rD+0), condT );
16501 getIRegA(rD+1), condT );
16506 assign(oldRd0, llGetIReg(rD+0));
16507 assign(oldRd1, llGetIReg(rD+1));
16513 putIRegA( rD+0, mkexpr(newRd0), IRTemp_INVALID, Ijk_Boring );
16517 putIRegA( rD+1, mkexpr(newRd1), IRTemp_INVALID, Ijk_Boring );
16527 vassert(rD+0 != rN); /* since we just wrote rD+0 */
16528 vassert(rD+1 != rN); /* since we just wrote rD+1 */
16536 case 1: DIP("%s%s r%u, %s\n", name, nCC(INSN_COND), rD, dis_buf);
16539 name, nCC(INSN_COND), rD, dis_buf);
16542 name, nCC(INSN_COND), rD, dis_buf);
16557 UInt rD = INSN(15,12);
16561 if (rN == 15/*it's {S,U}XTB*/ || rD == 15 || rM == 15) {
16574 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
16576 isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
16587 UInt rD = INSN(15,12);
16591 if (rN == 15/*it's {S,U}XTH*/ || rD == 15 || rM == 15) {
16604 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
16607 isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
16618 UInt rD = INSN(15,12);
16619 if (rM != 15 && rD != 15) {
16623 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
16625 nCC(INSN_COND), rD, rM);
16633 UInt rD = INSN(15,12);
16634 if (rM != 15 && rD != 15) {
16655 putIRegA(rD, mkexpr(irt_res), condT, Ijk_Boring);
16656 DIP("revsh%s r%u, r%u\n", nCC(INSN_COND), rD, rM);
16663 UInt rD = INSN(15,12);
16665 if (rD != 15 && rM != 15) {
16669 putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
16670 DIP("rbit r%u, r%u\n", rD, rM);
16680 UInt rD = INSN(19,16);
16683 if (rD != 15 && rM != 15 && rN != 15) {
16689 putIRegA(rD, res, condT, Ijk_Boring);
16691 nCC(INSN_COND), bitR ? "r" : "", rD, rN, rM);
16701 UInt rD = INSN(19,16);
16705 if (rD != 15 && rM != 15 && rN != 15) {
16713 putIRegA(rD, res, condT, Ijk_Boring);
16715 nCC(INSN_COND), bitR ? "r" : "", rD, rN, rM, rA);
17169 UInt rD = INSN(15,12);
17170 if (rD <= 14) {
17172 putIRegA(rD, IRExpr_Get(OFFB_TPIDRURO, Ity_I32),
17174 DIP("mrc%s p15,0, r%u, c13, c0, 3\n", nCC(INSN_COND), rD);
17860 /* ---------------- NEGS Rd, Rm ---------------- */
17861 /* Rd = -Rm */
17863 UInt rD = INSN0(2,0);
17868 // rD can never be r15
17869 putIRegT(rD, binop(Iop_Sub32, mkexpr(zero), mkexpr(arg)), condT);
17871 DIP("negs r%u, r%u\n", rD, rM);
17876 /* ---------------- MVNS Rd, Rm ---------------- */
17877 /* Rd = ~Rm */
17879 UInt rD = INSN0(2,0);
17886 // rD can never be r15
17887 putIRegT(rD, mkexpr(res), condT);
17890 DIP("mvns r%u, r%u\n", rD, rM);
17895 /* ---------------- ORRS Rd, Rm ---------------- */
17898 /* ---------------- ANDS Rd, Rm ---------------- */
17901 /* ---------------- EORS Rd, Rm ---------------- */
17904 /* ---------------- MULS Rd, Rm ---------------- */
17907 /* Rd = Rd `op` Rm */
17909 UInt rD = INSN0(2,0);
17915 assign( res, binop(anOp, getIRegT(rD
17917 // rD can never be r15
17918 putIRegT(rD, mkexpr(res), condT);
17921 DIP("%s r%u, r%u\n", anOpNm, rD, rM);
17926 /* ---------------- BICS Rd, Rm ---------------- */
17927 /* Rd = Rd & ~Rm */
17929 UInt rD = INSN0(2,0);
17935 assign( res, binop(Iop_And32, getIRegT(rD),
17938 // rD can never be r15
17939 putIRegT(rD, mkexpr(res), condT);
17942 DIP("bics r%u, r%u\n", rD, rM);
17947 /* ---------------- ADCS Rd, Rm ---------------- */
17948 /* Rd = Rd + Rm + oldC */
17950 UInt rD = INSN0(2,0);
17955 assign(argL, getIRegT(rD));
17961 // rD can never be r15
17962 putIRegT(rD, mkexpr(res), condT);
17965 DIP("adcs r%u, r%u\n", rD, rM);
17970 /* ---------------- SBCS Rd, Rm ---------------- */
17971 /* Rd = Rd - Rm - (oldC ^ 1) */
17973 UInt rD = INSN0(2,0);
17978 assign(argL, getIRegT(rD));
17984 // rD can never be r15
17985 putIRegT(rD, mkexpr(res), condT);
17988 DIP("sbcs r%u, r%u\n", rD, rM);
17993 /* ---------------- UXTB Rd, Rm ---------------- */
17994 /* Rd = 8Uto32(Rm) */
17996 UInt rD = INSN0(2,0);
17997 putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFF)),
17999 DIP("uxtb r%u, r%u\n", rD, rM);
18004 /* ---------------- SXTB Rd, Rm ---------------- */
18005 /* Rd = 8Sto32(Rm) */
18007 UInt rD = INSN0(2,0);
18008 putIRegT(rD, binop(Iop_Sar32,
18012 DIP("sxtb r%u, r%u\n", rD, rM);
18017 /* ---------------- UXTH Rd, Rm ---------------- */
18018 /* Rd = 16Uto32(Rm) */
18020 UInt rD = INSN0(2,0);
18021 putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFFFF)),
18023 DIP("uxth r%u, r%u\n", rD, rM);
18028 /* ---------------- SXTH Rd, Rm ---------------- */
18029 /* Rd = 16Sto32(Rm) */
18031 UInt rD = INSN0(2,0);
18032 putIRegT(rD, binop(Iop_Sar32,
18036 DIP("sxth r%u, r%u\n", rD, rM);
18044 /* ---------------- LSLS Rs, Rd ---------------- */
18045 /* ---------------- LSRS Rs, Rd ---------------- */
18046 /* ---------------- ASRS Rs, Rd ---------------- */
18047 /* ---------------- RORS Rs, Rd ---------------- */
18048 /* Rd = Rd `op` Rs, and set flags */
18050 UInt rD = INSN0(2,0);
18058 assign(rDt, getIRegT(rD));
18064 dis_buf, &res, &resC, rDt, rSt, rD, rS
18070 dis_buf, &res, &resC, rDt, rSt, rD, rS
18076 dis_buf, &res, &resC, rDt, rSt, rD, rS
18082 dis_buf, &res, &resC, rDt, rSt, rD, rS
18090 putIRegT(rD, mkexpr(res), condT);
18093 DIP("%ss r%u, r%u\n", wot, rS, rD);
18099 /* ---------------- REV Rd, Rm ---------------- */
18100 /* ---------------- REV16 Rd, Rm ---------------- */
18102 UInt rD = INSN0(2,0);
18107 putIRegT(rD, mkexpr(res), condT);
18108 DIP("rev%s r%u, r%u\n", isREV ? "" : "16", rD, rM);
18113 /* ---------------- REVSH Rd, Rn ---------------- */
18115 UInt rD = INSN0(2,0);
18136 putIRegT(rD, mkexpr(irt_res), condT);
18137 DIP("revsh r%u, r%u\n", rD, rM);
18255 /* ---------------- ADD(HI) Rd, Rm ---------------- */
18259 UInt rD = (h1 << 3) | INSN0(2,0);
18261 if (rD == 15 && rM == 15) {
18265 assign( res, binop(Iop_Add32, getIRegT(rD), getIRegT(rM) ));
18266 if (rD != 15) {
18267 putIRegT( rD, mkexpr(res), condT );
18280 DIP("add(hi) r%u, r%u\n", rD, rM);
18287 /* ---------------- CMP(HI) Rd, Rm ---------------- */
18306 /* ---------------- MOV(HI) Rd, Rm ---------------- */
18310 UInt rD = (h1 << 3) | INSN0(2,0);
18311 /* The old ARM ARM seems to disallow the case where both Rd and
18316 if (rD != 15) {
18317 putIRegT( rD, mkexpr(val), condT );
18330 DIP("mov r%u, r%u\n", rD, rM);
18545 /* ---------------- ADDS Rd, Rn, #uimm3 ---------------- */
18546 /* ---------------- SUBS Rd, Rn, #uimm3 ---------------- */
18549 UInt rD = INSN0(2,0);
18555 putIRegT(rD, binop(isSub ? Iop_Sub32 : Iop_Add32,
18560 DIP("%s r%u, r%u, #%u\n", isSub ? "subs" : "adds", rD, rN, uimm3);
18566 /* ---------------- ADDS Rd, Rn, Rm ---------------- */
18567 /* ---------------- SUBS Rd, Rn, Rm ---------------- */
18570 UInt rD = INSN0(2,0);
18576 putIRegT( rD, binop(isSub ? Iop_Sub32 : Iop_Add32,
18581 DIP("%s r%u, r%u, r%u\n", isSub ? "subs" : "adds", rD, rN, rM);
18587 /* ------------- LDR Rd, [Rn, Rm] ------------- */
18588 /* ------------- STR Rd, [Rn, Rm] ------------- */
18589 /* LDR/STR Rd, [Rn + Rm] */
18590 UInt rD = INSN0(2,0);
18599 loadGuardedLE( tD, ILGop_Ident32, ea, llGetIReg(rD), condT );
18600 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
18602 storeGuardedLE(ea, getIRegT(rD), condT);
18606 DIP("%s r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
18612 /* ------------- LDRH Rd, [Rn, Rm] ------------- */
18613 /* ------------- STRH Rd, [Rn, Rm] ------------- */
18614 /* LDRH/STRH Rd, [Rn + Rm] */
18615 UInt rD = INSN0(2,0);
18624 loadGuardedLE(tD, ILGop_16Uto32, ea, llGetIReg(rD), condT);
18625 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
18627 storeGuardedLE( ea, unop(Iop_32to16, getIRegT(rD)), condT );
18631 DIP("%sh r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
18636 /* ------------- LDRSH Rd, [Rn, Rm] ------------- */
18637 /* LDRSH Rd, [Rn + Rm] */
18638 UInt rD = INSN0(2,0);
18645 loadGuardedLE(tD, ILGop_16Sto32, ea, llGetIReg(rD), condT);
18646 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
18649 DIP("ldrsh r%u, [r%u, r%u]\n", rD, rN, rM);
18654 /* ------------- LDRSB Rd, [Rn, Rm] ------------- */
18655 /* LDRSB Rd, [Rn + Rm] */
18656 UInt rD = INSN0(2,0);
18663 loadGuardedLE(tD, ILGop_8Sto32, ea, llGetIReg(rD), condT);
18664 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
18667 DIP("ldrsb r%u, [r%u, r%u]\n", rD, rN, rM);
18673 /* ------------- LDRB Rd, [Rn, Rm] ------------- */
18674 /* ------------- STRB Rd, [Rn, Rm] ------------- */
18675 /* LDRB/STRB Rd, [Rn + Rm] */
18676 UInt rD = INSN0(2,0);
18685 loadGuardedLE(tD, ILGop_8Uto32, ea, llGetIReg(rD), condT);
18686 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
18688 storeGuardedLE( ea, unop(Iop_32to8, getIRegT(rD)), condT );
18692 DIP("%sb r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
18726 /* ---------------- ADD rD, PC, #imm8 * 4 ---------------- */
18728 /* rD = align4(PC) + imm8 * 4 */
18729 UInt rD = INSN0(10,8);
18731 putIRegT(rD, binop(Iop_Add32,
18735 DIP("add r%u, pc, #%u\n", rD, imm8 * 4);
18740 /* ---------------- ADD rD, SP, #imm8 * 4 ---------------- */
18741 UInt rD = INSN0(10,8);
18743 putIRegT(rD, binop(Iop_Add32, getIRegT(13), mkU32(imm8 * 4)),
18745 DIP("add r%u, r13, #%u\n", rD, imm8 * 4);
18765 UInt rD = INSN0(10,8);
18773 putIRegT(rD, mkexpr(res), condT);
18776 DIP("movs r%u, #%u\n", rD, uimm8);
18781 /* ------------- LDR Rd, [PC, #imm8 * 4] ------------- */
18782 /* LDR Rd, [align4(PC) + imm8 * 4] */
18783 UInt rD = INSN0(10,8);
18792 loadGuardedLE( tD, ILGop_Ident32, mkexpr(ea), llGetIReg(rD), condT );
18793 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
18796 DIP("ldr r%u, [pc, #%u]\n", rD, imm8 * 4);
18802 /* ------------- LDR Rd, [Rn, #imm5 * 4] ------------- */
18803 /* ------------- STR Rd, [Rn, #imm5 * 4] ------------- */
18804 /* LDR/STR Rd, [Rn + imm5 * 4] */
18805 UInt rD = INSN0(2,0);
18814 loadGuardedLE( tD, ILGop_Ident32, ea, llGetIReg(rD), condT );
18815 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
18817 storeGuardedLE( ea, getIRegT(rD), condT );
18821 DIP("%s r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5 * 4);
18827 /* ------------- LDRH Rd, [Rn, #imm5 * 2] ------------- */
18828 /* ------------- STRH Rd, [Rn, #imm5 * 2] ------------- */
18829 /* LDRH/STRH Rd, [Rn + imm5 * 2] */
18830 UInt rD = INSN0(2,0);
18839 loadGuardedLE( tD, ILGop_16Uto32, ea, llGetIReg(rD), condT );
18840 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
18842 storeGuardedLE( ea, unop(Iop_32to16, getIRegT(rD)), condT );
18846 DIP("%sh r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5 * 2);
18852 /* ------------- LDRB Rd, [Rn, #imm5] ------------- */
18853 /* ------------- STRB Rd, [Rn, #imm5] ------------- */
18854 /* LDRB/STRB Rd, [Rn + imm5] */
18855 UInt rD = INSN0(2,0);
18864 loadGuardedLE( tD, ILGop_8Uto32, ea, llGetIReg(rD), condT );
18865 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
18867 storeGuardedLE( ea, unop(Iop_32to8, getIRegT(rD)), condT );
18871 DIP("%sb r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5);
18877 /* ------------- LDR Rd, [SP, #imm8 * 4] ------------- */
18878 /* ------------- STR Rd, [SP, #imm8 * 4] ------------- */
18879 /* LDR/STR Rd, [SP + imm8 * 4] */
18880 UInt rD = INSN0(10,8);
18888 loadGuardedLE( tD, ILGop_Ident32, ea, llGetIReg(rD), condT );
18889 putIRegT(rD, mkexpr(tD), IRTemp_INVALID);
18891 storeGuardedLE(ea, getIRegT(rD), condT);
18895 DIP("%s r%u, [sp, #%u]\n", isLD ? "ldr" : "str", rD, imm8 * 4);
18994 /* ---------------- LSLS Rd, Rm, #imm5 ---------------- */
18995 /* ---------------- LSRS Rd, Rm, #imm5 ---------------- */
18996 /* ---------------- ASRS Rd, Rm, #imm5 ---------------- */
18997 UInt rD = INSN0(2,0);
19032 putIRegT(rD, mkexpr(res), condT);
19036 DIP("%ss r%u, r%u, #%u\n", wot, rD, rM, imm5);
19274 /* -------------- (T3) ADD{S}.W Rd, Rn, #constT -------------- */
19280 UInt rD = INSN1(11,8);
19281 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
19283 if (!valid && rD <= 14 && rN == 13)
19293 putIRegT(rD, mkexpr(res), condT);
19297 bS == 1 ? "s" : "", rD, rN, imm32);
19302 /* ---------------- (T4) ADDW Rd, Rn, #uimm12 -------------- */
19307 UInt rD = INSN1(11,8);
19308 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
19310 rD <= 14 && rN == 13)
19320 putIRegT(rD, mkexpr(res), condT);
19321 DIP("addw r%u, r%u, #%u\n", rD, rN, imm12);
19379 /* -------------- (T3) SUB{S}.W Rd, Rn, #constT -------------- */
19380 /* -------------- (T3) RSB{S}.W Rd, Rn, #constT -------------- */
19388 UInt rD = INSN1(11,8);
19389 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
19392 if (!valid && !isRSB && rN == 13 && rD != 15)
19404 putIRegT(rD, mkexpr(res), condT);
19412 isRSB ? "rsb" : "sub", bS == 1 ? "s" : "", rD, rN, imm32);
19417 /* -------------- (T4) SUBW Rd, Rn, #uimm12 ------------------- */
19422 UInt rD = INSN1(11,8);
19423 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
19425 if (!valid && rD == 13 && rN == 13)
19435 putIRegT(rD, mkexpr(res), condT);
19436 DIP("subw r%u, r%u, #%u\n", rD, rN, imm12);
19441 /* -------------- (T1) ADC{S}.W Rd, Rn, #constT -------------- */
19442 /* -------------- (T1) SBC{S}.W Rd, Rn, #constT -------------- */
19447 /* ADC: Rd = Rn + constT + oldC */
19448 /* SBC: Rd = Rn - constT - (oldC ^ 1) */
19451 UInt rD = INSN1(11,8);
19452 if (!isBadRegT(rN) && !isBadRegT(rD)) {
19469 putIRegT(rD, mkexpr(res), condT);
19480 putIRegT(rD, mkexpr(res), condT);
19489 nm, bS == 1 ? "s" : "", rD, rN, imm32);
19494 /* -------------- (T1) ORR{S}.W Rd, Rn, #constT -------------- */
19495 /* -------------- (T1) AND{S}.W Rd, Rn, #constT -------------- */
19496 /* -------------- (T1) BIC{S}.W Rd, Rn, #constT -------------- */
19497 /* -------------- (T1) EOR{S}.W Rd, Rn, #constT -------------- */
19507 UInt rD = INSN1(11,8);
19508 if (!isBadRegT(rN) && !isBadRegT(rD)) {
19530 putIRegT(rD, mkexpr(res), condT);
19542 nm, bS == 1 ? "s" : "", rD, rN, imm32);
19547 /* ---------- (T3) ADD{S}.W Rd, Rn, Rm, {shift} ---------- */
19548 /* ---------- (T3) SUB{S}.W Rd, Rn, Rm, {shift} ---------- */
19549 /* ---------- (T3) RSB{S}.W Rd, Rn, Rm, {shift} ---------- */
19556 UInt rD = INSN1(11,8);
19562 Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM);
19566 && rD != 15 && rN == 13 && imm5 <= 3 && how == 0) {
19572 && rD != 15 && rN == 13 && imm5 == 0 && how == 0) {
19603 putIRegT(rD, mkexpr(res), condT);
19621 nm, bS ? "s" : "", rD, rN, dis_buf);
19626 /* ---------- (T3) ADC{S}.W Rd, Rn, Rm, {shift} ---------- */
19627 /* ---------- (T2) SBC{S}.W Rd, Rn, Rm, {shift} ---------- */
19632 /* ADC: Rd = Rn + shifter_operand + oldC */
19633 /* SBC: Rd = Rn - shifter_operand - (oldC ^ 1) */
19635 UInt rD = INSN1(11,8);
19637 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
19665 putIRegT(rD, mkexpr(res), condT);
19676 putIRegT(rD, mkexpr(res), condT);
19686 nm, bS ? "s" : "", rD, rN, dis_buf);
19691 /* ---------- (T3) AND{S}.W Rd, Rn, Rm, {shift} ---------- */
19692 /* ---------- (T3) ORR{S}.W Rd, Rn, Rm, {shift} ---------- */
19693 /* ---------- (T3) EOR{S}.W Rd, Rn, Rm, {shift} ---------- */
19694 /* ---------- (T3) BIC{S}.W Rd, Rn, Rm, {shift} ---------- */
19695 /* ---------- (T1) ORN{S}.W Rd, Rn, Rm, {shift} ---------- */
19704 UInt rD = INSN1(11,8);
19706 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
19746 putIRegT(rD, mkexpr(res), condT);
19755 nm, bS ? "s" : "", rD, rN, dis_buf);
19760 /* -------------- (T?) LSL{S}.W Rd, Rn, Rm -------------- */
19761 /* -------------- (T?) LSR{S}.W Rd, Rn, Rm -------------- */
19762 /* -------------- (T?) ASR{S}.W Rd, Rn, Rm -------------- */
19763 /* -------------- (T?) ROR{S}.W Rd, Rn, Rm -------------- */
19769 UInt rD = INSN1(11,8);
19772 Bool valid = !isBadRegT(rN) && !isBadRegT(rM) && !isBadRegT(rD);
19789 putIRegT(rD, mkexpr(res), condT);
19795 nm, bS ? "s" : "", rD, rN, rM);
19800 /* ------------ (T?) MOV{S}.W Rd, Rn, {shift} ------------ */
19801 /* ------------ (T?) MVN{S}.W Rd, Rn, {shift} ------------ */
19804 UInt rD = INSN1(11,8);
19807 int badRegs = bS ? (isBadRegT(rD) || isBadRegT(rN))
19808 : (rD == 15 || rN == 15 || (rD == 15 && rN == 15));
19828 putIRegT(rD, mkexpr(res), condT);
19835 isMVN ? "mvn" : "mov", bS ? "s" : "", rD, dis_buf);
19914 /* -------------- (T2) MOV{S}.W Rd, #constT -------------- */
19915 /* -------------- (T2) MVN{S}.W Rd, #constT -------------- */
19921 UInt rD = INSN1(11,8);
19922 if (!isBadRegT(rD)) {
19929 putIRegT(rD, mkexpr(res), condT);
19941 isMVN ? "mvn" : "mov", bS ? "s" : "", rD, imm32);
19946 /* -------------- (T3) MOVW Rd, #imm16 -------------- */
19950 UInt rD = INSN1(11,8);
19951 if (!isBadRegT(rD)) {
19954 putIRegT(rD, mkU32(imm16), condT);
19955 DIP("movw r%u, #%u\n", rD, imm16);
19960 /* ---------------- MOVT Rd, #imm16 ---------------- */
19964 UInt rD = INSN1(11,8);
19965 if (!isBadRegT(rD)) {
19971 binop(Iop_And32, getIRegT(rD), mkU32(0xFFFF)),
19973 putIRegT(rD, mkexpr(res), condT);
19974 DIP("movt r%u, #%u\n", rD, imm16);
20515 strd rD, [sp, #-8]
20710 UInt rD = INSN1(11,8);
20714 if (!isBadRegT(rD) && !isBadRegT(rN) && msb <= 31) {
20731 putIRegT(rD, mkexpr(res), condT);
20734 isU ? "ubfx" : "sbfx", rD, rN, lsb, wm1 + 1);
20755 UInt rD = INSN1(11,8);
20758 if (!isBadRegT(rD) && !isBadRegT(rM)) {
20814 putIRegT(rD, mkexpr(dstT), condT);
20815 DIP("%s r%u, r%u, ror #%u\n", nm, rD, rM, 8 * rot);
20820 /* -------------- MUL.W Rd, Rn, Rm -------------- */
20824 UInt rD = INSN1(11,8);
20826 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
20829 putIRegT(rD, mkexpr(res), condT);
20830 DIP("mul.w r%u, r%u, r%u\n", rD, rN, rM);
20835 /* -------------- SDIV.W Rd, Rn, Rm -------------- */
20839 UInt rD = INSN1(11,8);
20841 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
20848 putIRegT(rD, mkexpr(res), condT);
20849 DIP("sdiv.w r%u, r%u, r%u\n", rD, rN, rM);
20854 /* -------------- UDIV.W Rd, Rn, Rm -------------- */
20858 UInt rD = INSN1(11,8);
20860 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
20867 putIRegT(rD, mkexpr(res), condT);
20868 DIP("udiv.w r%u, r%u, r%u\n", rD, rN, rM);
20900 UInt rD = INSN1(11,8);
20902 if (!isBadRegT(rD) && !isBadRegT(rN)
20910 putIRegT(rD, mkexpr(res), condT);
20912 isMLA ? "mla" : "mls", rD, rN, rM, rA);
20920 /* rD = align4(PC) + imm32 */
20921 UInt rD = INSN1(11,8);
20922 if (!isBadRegT(rD)) {
20925 putIRegT(rD, binop(Iop_Add32,
20929 DIP("add r%u, pc, #%u\n", rD, imm32);
21009 UInt rD = INSN1(11,8);
21012 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
21018 putIRegT(rD, res, condT);
21020 bitR ? "r" : "", rD, rN, rM);
21031 UInt rD = INSN1(11,8);
21034 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && (rA != 13)) {
21042 putIRegT(rD, res, condT);
21044 bitR ? "r" : "", rD, rN, rM, rA);
21052 /* rD = align4(PC) - imm32 */
21053 UInt rD = INSN1(11,8);
21054 if (!isBadRegT(rD)) {
21057 putIRegT(rD, binop(Iop_Sub32,
21061 DIP("sub r%u, pc, #%u\n", rD, imm32);
21069 UInt rD = INSN1(11,8);
21073 if (isBadRegT(rD) || rN == 13 || msb < lsb) {
21085 assign(olddst, getIRegT(rD));
21096 putIRegT(rD, mkexpr(newdst), condT);
21100 rD, lsb, msb-lsb+1);
21103 rD, rN, lsb, msb-lsb+1);
21117 UInt rD = INSN1(11,8);
21120 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
21131 putIRegT(rD, mkexpr(res), condT);
21133 isU ? 'u' : 's', rD, rN, rM, rot);
21146 UInt rD = INSN1(11,8);
21149 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
21160 putIRegT(rD, mkexpr(res), condT);
21162 isU ? 'u' : 's', rD, rN, rM, rot);
21172 UInt rD = INSN1(11,8);
21174 if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) {
21183 putIRegT(rD, mkexpr(res), condT);
21184 DIP("clz r%u, r%u\n", rD, rM1);
21194 UInt rD = INSN1(11,8);
21196 if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) {
21200 putIRegT(rD, mkexpr(res), condT);
21201 DIP("rbit r%u, r%u\n", rD, rM1);
21213 UInt rD = INSN1(11,8);
21216 if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) {
21220 putIRegT(rD, mkexpr(res), condT);
21221 DIP("rev%s r%u, r%u\n", isREV ? "" : "16", rD, rM1);
21232 UInt rD = INSN1(11,8);
21233 if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) {
21254 putIRegT(rD, mkexpr(irt_res), condT);
21255 DIP("revsh r%u, r%u\n", rD, rM1);
21279 UInt rD = INSN1(11,8);
21280 if (!isBadRegT(rD)) {
21282 putIRegT( rD, mkexpr(apsr), condT );
21283 DIP("mrs r%u, cpsr\n", rD);
21356 UInt rD = INSN1(11,8);
21358 if (!isBadRegT(rD) && !isBadRegT(rT) && rN != 15
21359 && rD != rN && rD != rT) {
21370 /* Set rD to 1 on failure, 0 on success. Currently we have
21375 putIRegT(rD, mkexpr(resSC32), IRTemp_INVALID);
21376 DIP("strex r%u, r%u, [r%u, #+%u]\n", rD, rT, rN, imm8 * 4);
21386 UInt rD = INSN1(3,0);
21388 if (!isBadRegT(rD) && !isBadRegT(rT) && rN != 15
21389 && rD != rN && rD != rT) {
21399 /* Set rD to 1 on failure, 0 on success. Currently we have
21404 putIRegT(rD, mkexpr(resSC32), IRTemp_INVALID);
21405 DIP("strex%c r%u, r%u, [r%u]\n", isH ? 'h' : 'b', rD, rT, rN);
21415 UInt rD = INSN1(3,0);
21416 if (!isBadRegT(rD) && !isBadRegT(rT) && !isBadRegT(rT2)
21417 && rN != 15 && rD != rN && rD != rT && rD != rT) {
21429 /* Set rD to 1 on failure, 0 on success. Currently we have
21434 putIRegT(rD, mkexpr(resSC32), IRTemp_INVALID);
21435 DIP("strexd r%u, r%u, r%u, [r%u]\n", rD, rT, rT2, rN);
21523 UInt rD = INSN1(15,12);
21524 if (!isBadRegT(rD)) {
21525 putIRegT(rD, IRExpr_Get(OFFB_TPIDRURO, Ity_I32), IRTemp_INVALID);
21526 DIP("mrc p15,0, r%u, c13, c0, 3\n", rD);
