Lines Matching refs:vHi
1630 HReg vHi, vLo, vec;
1631 iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg);
1639 case Iop_V256to64_2: vec = vHi; off = -16; break;
1640 case Iop_V256to64_3: vec = vHi; off = -8; break;
3304 HReg vHi, vLo;
3305 iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg);
3306 return (e->Iex.Unop.op == Iop_V256toV128_1) ? vHi : vLo;
3751 HReg vHi = newVRegV(env);
3757 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, am16));
3758 *rHi = vHi;
3764 HReg vHi = newVRegV(env);
3770 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, am16));
3771 *rHi = vHi;
3780 HReg vHi = generate_zeroes_V128(env);
3782 addInstr(env, mk_vMOVsd_RR(vHi, vLo));
3783 *rHi = vHi;
4230 HReg vHi = newVRegV(env);
4243 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, m16_rsp));
4248 *rHi = vHi;
4336 HReg vHi, vLo;
4337 iselDVecExpr(&vHi, &vLo, env, stmt->Ist.Store.data);
4339 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vHi, am16));
4392 HReg vHi, vLo;
4393 iselDVecExpr(&vHi, &vLo, env, stmt->Ist.Put.data);
4398 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vHi, am16));