Lines Matching refs:VBinV
1632 i->ARM64in.VBinV.op = op;
1633 i->ARM64in.VBinV.dst = dst;
1634 i->ARM64in.VBinV.argL = argL;
1635 i->ARM64in.VBinV.argR = argR;
2278 showARM64VecBinOp(&nm, &ar, i->ARM64in.VBinV.op);
2280 ppHRegARM64(i->ARM64in.VBinV.dst);
2282 ppHRegARM64(i->ARM64in.VBinV.argL);
2284 ppHRegARM64(i->ARM64in.VBinV.argR);
2779 addHRegUse(u, HRmWrite, i->ARM64in.VBinV.dst);
2780 addHRegUse(u, HRmRead, i->ARM64in.VBinV.argL);
2781 addHRegUse(u, HRmRead, i->ARM64in.VBinV.argR);
3069 i->ARM64in.VBinV.dst = lookupHRegRemap(m, i->ARM64in.VBinV.dst);
3070 i->ARM64in.VBinV.argL = lookupHRegRemap(m, i->ARM64in.VBinV.argL);
3071 i->ARM64in.VBinV.argR = lookupHRegRemap(m, i->ARM64in.VBinV.argR);
5064 UInt vD = qregNo(i->ARM64in.VBinV.dst);
5065 ARM64VecBinOp op = i->ARM64in.VBinV.op;
5069 UInt vN = isV128 ? qregNo(i->ARM64in.VBinV.argL)
5070 : dregNo(i->ARM64in.VBinV.argL);
5071 UInt vM = isV128 ? qregNo(i->ARM64in.VBinV.argR)
5072 : dregNo(i->ARM64in.VBinV.argR);
5073 switch (i->ARM64in.VBinV.op) {
