Lines Matching refs:VUnaryS
1582 i->ARM64in.VUnaryS.op = op;
1583 i->ARM64in.VUnaryS.dst = dst;
1584 i->ARM64in.VUnaryS.src = src;
2232 vex_printf("f%s ", showARM64FpUnaryOp(i->ARM64in.VUnaryS.op));
2233 ppHRegARM64asSreg(i->ARM64in.VUnaryS.dst);
2235 ppHRegARM64asSreg(i->ARM64in.VUnaryS.src);
2751 addHRegUse(u, HRmWrite, i->ARM64in.VUnaryS.dst);
2752 addHRegUse(u, HRmRead, i->ARM64in.VUnaryS.src);
2801 //ZZ addHRegUse(u, HRmWrite, i->ARMin.VUnaryS.dst);
2802 //ZZ addHRegUse(u, HRmRead, i->ARMin.VUnaryS.src);
3044 i->ARM64in.VUnaryS.dst = lookupHRegRemap(m, i->ARM64in.VUnaryS.dst);
3045 i->ARM64in.VUnaryS.src = lookupHRegRemap(m, i->ARM64in.VUnaryS.src);
4897 UInt sD = dregNo(i->ARM64in.VUnaryS.dst);
4898 UInt sN = dregNo(i->ARM64in.VUnaryS.src);
4901 switch (i->ARM64in.VUnaryS.op) {
4915 if (i->ARM64in.VUnaryS.op == ARM64fpu_RINT) {
5489 //ZZ UInt fD = fregNo(i->ARMin.VUnaryS.dst);
5490 //ZZ UInt fM = fregNo(i->ARMin.VUnaryS.src);
5492 //ZZ switch (i->ARMin.VUnaryS.op) {
