Lines Matching refs:rD
1386 ARM64Instr* ARM64Instr_LdSt64 ( Bool isLoad, HReg rD
1390 i->ARM64in.LdSt64.rD = rD;
1394 ARM64Instr* ARM64Instr_LdSt32 ( Bool isLoad, HReg rD, ARM64AMode* amode ) {
1398 i->ARM64in.LdSt32.rD = rD;
1402 ARM64Instr* ARM64Instr_LdSt16 ( Bool isLoad, HReg rD, ARM64AMode* amode ) {
1406 i->ARM64in.LdSt16.rD = rD;
1410 ARM64Instr* ARM64Instr_LdSt8 ( Bool isLoad, HReg rD, ARM64AMode* amode ) {
1414 i->ARM64in.LdSt8.rD = rD;
1544 ARM64Instr* ARM64Instr_VCvtI2F ( ARM64CvtOp how, HReg rD, HReg rS ) {
1548 i->ARM64in.VCvtI2F.rD = rD;
1552 ARM64Instr* ARM64Instr_VCvtF2I ( ARM64CvtOp how, HReg rD, HReg rS,
1557 i->ARM64in.VCvtF2I.rD = rD;
1804 ARM64Instr* ARM64Instr_VDfromX ( HReg rD, HReg rX ) {
1807 i->ARM64in.VDfromX.rD = rD;
1900 //ZZ ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) {
1907 //ZZ i->ARMin.Alu.dst = rD;
1912 //ZZ i->ARMin.Add32.rD = rD;
1994 ppHRegARM64(i->ARM64in.LdSt64.rD);
2001 ppHRegARM64(i->ARM64in.LdSt64.rD);
2007 ppHRegARM64(i->ARM64in.LdSt32.rD);
2014 ppHRegARM64(i->ARM64in.LdSt32.rD);
2020 ppHRegARM64(i->ARM64in.LdSt16.rD);
2027 ppHRegARM64(i->ARM64in.LdSt16.rD);
2033 ppHRegARM64(i->ARM64in.LdSt8.rD);
2040 ppHRegARM64(i->ARM64in.LdSt8.rD);
2192 ppHRegARM64(i->ARM64in.VCvtI2F.rD);
2207 ppHRegARM64(i->ARM64in.VCvtF2I.rD);
2478 ppHRegARM64(i->ARM64in.VDfromX.rD);
2519 //ZZ ppHRegARM(i->ARMin.Add32.rD);
2596 addHRegUse(u, HRmWrite, i->ARM64in.LdSt64.rD);
2598 addHRegUse(u, HRmRead, i->ARM64in.LdSt64.rD);
2604 addHRegUse(u, HRmWrite, i->ARM64in.LdSt32.rD);
2606 addHRegUse(u, HRmRead, i->ARM64in.LdSt32.rD);
2612 addHRegUse(u, HRmWrite, i->ARM64in.LdSt16.rD);
2614 addHRegUse(u, HRmRead, i->ARM64in.LdSt16.rD);
2620 addHRegUse(u, HRmWrite, i->ARM64in.LdSt8.rD);
2622 addHRegUse(u, HRmRead, i->ARM64in.LdSt8.rD);
2736 addHRegUse(u, HRmWrite, i->ARM64in.VCvtI2F.rD);
2740 addHRegUse(u, HRmWrite, i->ARM64in.VCvtF2I.rD);
2872 addHRegUse(u, HRmWrite, i->ARM64in.VDfromX.rD);
2901 //ZZ addHRegUse(u, HRmWrite, i->ARMin.Add32.rD);
2962 i->ARM64in.LdSt64.rD = lookupHRegRemap(m, i->ARM64in.LdSt64.rD);
2966 i->ARM64in.LdSt32.rD = lookupHRegRemap(m, i->ARM64in.LdSt32.rD);
2970 i->ARM64in.LdSt16.rD = lookupHRegRemap(m, i->ARM64in.LdSt16.rD);
2974 i->ARM64in.LdSt8.rD = lookupHRegRemap(m, i->ARM64in.LdSt8.rD);
3029 i->ARM64in.VCvtI2F.rD = lookupHRegRemap(m, i->ARM64in.VCvtI2F.rD);
3033 i->ARM64in.VCvtF2I.rD = lookupHRegRemap(m, i->ARM64in.VCvtF2I.rD);
3144 i->ARM64in.VDfromX.rD
3145 = lookupHRegRemap(m, i->ARM64in.VDfromX.rD);
3178 //ZZ i->ARMin.Add32.rD = lookupHRegRemap(m, i->ARMin.Add32.rD);
3814 rD, using the given amode for the address. */
3863 rD, using the given amode for the address. */
3912 rD, using the given amode for the address. */
4032 UInt rD = iregNo(i->ARM64in.Arith.dst);
4041 argR->ARM64riA.I12.imm12, rN, rD
4048 X01011000, rM, X000000, rN, rD
4058 UInt rD = 31; /* XZR, we are going to dump the result */
4064 /* 1 11 10001 sh imm12 Rn Rd = SUBS Xd, Xn, #imm */
4065 /* 0 11 10001 sh imm12 Rn Rd = SUBS Wd, Wn, #imm */
4069 argR->ARM64riA.I12.imm12, rN, rD);
4072 /* 1 11 01011 00 0 Rm 000000 Rn Rd = SUBS Xd, Xn, Xm */
4073 /* 0 11 01011 00 0 Rm 000000 Rn Rd = SUBS Wd, Wn, Wm */
4076 X01011000, rM, X000000, rN, rD);
4085 UInt rD = iregNo(i->ARM64in.Logic.dst);
4089 vassert(rD < 31);
4100 /* 1 01 100100 N immR immS Rn Rd = ORR <Xd|Sp>, Xn, #imm */
4101 /* 1 00 100100 N immR immS Rn Rd = AND <Xd|Sp>, Xn, #imm */
4102 /* 1 10 100100 N immR immS Rn Rd = EOR <Xd|Sp>, Xn, #imm */
4106 rN, rD
4116 *p++ = X_3_8_5_6_5_5(opc, X01010000, rM, X000000, rN, rD);
4125 UInt rD = 31; /* XZR, we are going to dump the result */
4130 /* 1 11 100100 N immR immS Rn Rd = ANDS Xd, Xn, #imm */
4134 rN, rD
4144 UInt rD = iregNo(i->ARM64in.Shift.dst);
4147 vassert(rD < 31);
4159 1, 64-sh, 63-sh, rN, rD);
4162 *p++ = X_3_6_1_6_6_5_5(X110, X100110, 1, sh, 63, rN, rD);
4165 *p++ = X_3_6_1_6_6_5_5(X100, X100110, 1, sh, 63, rN, rD);
4185 *p++ = X_3_8_5_6_5_5(X100, X11010110, rM, subOpc, rN, rD);
4237 iregNo(i->ARM64in.LdSt64.rD),
4243 iregNo(i->ARM64in.LdSt32.rD),
4249 iregNo(i->ARM64in.LdSt16.rD),
4255 iregNo(i->ARM64in.LdSt8.rD),
4262 //ZZ HReg rD;
4269 //ZZ rD = i->ARMin.LdSt32.rD;
4275 //ZZ rD = i->ARMin.LdSt8U.rD;
4292 //ZZ iregNo(rD));
4302 //ZZ HReg rD = i->ARMin.LdSt16.rD;
4326 //ZZ iregNo(rD), imm8hi, X1011, imm8lo);
4333 //ZZ iregNo(rD), imm8hi, X1011, imm8lo);
4340 //ZZ iregNo(rD), imm8hi, X1111, imm8lo);
4351 //ZZ HReg rD = i->ARMin.Ld8S.rD;
4371 //ZZ iregNo(rD), imm8hi, X1101, imm8lo);
4756 UInt rD = dregNo(i->ARM64in.VCvtI2F.rD);
4761 *p++ = X_3_5_8_6_5_5(X000, X11110, X00100010, X000000, rN, rD);
4764 *p++ = X_3_5_8_6_5_5(X000, X11110, X01100010, X000000, rN, rD);
4767 *p++ = X_3_5_8_6_5_5(X100, X11110, X00100010, X000000, rN, rD);
4770 *p++ = X_3_5_8_6_5_5(X100, X11110, X01100010, X000000, rN, rD);
4773 *p++ = X_3_5_8_6_5_5(X000, X11110, X00100011, X000000, rN, rD);
4776 *p++ = X_3_5_8_6_5_5(X000, X11110, X01100011, X000000, rN, rD);
4779 *p++ = X_3_5_8_6_5_5(X100, X11110, X00100011, X000000, rN, rD);
4782 *p++ = X_3_5_8_6_5_5(X100, X11110, X01100011, X000000, rN, rD);
4791 sf 00,11110,0x 1 00 000,000000 n d FCVTNS Rd, Fn (round to
4792 sf 00,11110,0x 1 00 001,000000 n d FCVTNU Rd, Fn nearest)
4797 Rd is Xd when sf==1, Wd when sf==0
4801 UInt rD = iregNo(i->ARM64in.VCvtF2I.rD);
4809 X000000, rN, rD);
4813 X000000, rN, rD);
4817 X000000, rN, rD);
4821 X000000, rN, rD);
4825 X000000, rN, rD);
4829 X000000, rN, rD);
4833 X000000, rN, rD);
4837 X000000, rN, rD);
6344 /* movi rD, #0xFF == 0x2F 0x00 0xE4 001 rD */
6350 /* movi rD, #0xFFFF == 0x2F 0x00 0xE4 011 rD */
6356 /* movi rD, #0xFFFFFFFF == 0x2F 0x00 0xE5 111 rD */
6362 /* movi rD, #0xFFFFFFFFFFFFFFFF == 0x2F 0x07 0xE7 111 rD */
6376 UInt dd = dregNo(i->ARM64in.VDfromX.rD);
6417 HReg rD = i->ARM64in.VMov.dst;
6421 UInt dd = dregNo(rD);
6498 //ZZ UInt regD = iregNo(i->ARMin.Add32.rD);
