Lines Matching refs:sD
1516 ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) {
1520 i->ARM64in.VLdStS.sD = sD;
2149 ppHRegARM64asSreg(i->ARM64in.VLdStS.sD);
2158 ppHRegARM64asSreg(i->ARM64in.VLdStS.sD);
2714 addHRegUse(u, HRmWrite, i->ARM64in.VLdStS.sD);
2716 addHRegUse(u, HRmRead, i->ARM64in.VLdStS.sD);
3016 i->ARM64in.VLdStS.sD = lookupHRegRemap(m, i->ARM64in.VLdStS.sD);
4699 UInt sD = dregNo(i->ARM64in.VLdStS.sD);
4706 vassert(sD < 32);
4709 uimm12, rN, sD);
4746 000 11110 00 1 00 010 000000 n d SCVTF Sd, Wn
4748 100 11110 00 1 00 010 000000 n d SCVTF Sd, Xn
4750 000 11110 00 1 00 011 000000 n d UCVTF Sd, Wn
4752 100 11110 00 1 00 011 000000 n d UCVTF Sd, Xn
4760 case ARM64cvt_F32_I32S: /* SCVTF Sd, Wn */
4766 case ARM64cvt_F32_I64S: /* SCVTF Sd, Xn */
4772 case ARM64cvt_F32_I32U: /* UCVTF Sd, Wn */
4778 case ARM64cvt_F32_I64U: /* UCVTF Sd, Xn */
4847 ---------- 01 ----- 0,0 --------- FCVT Sd, Dn (D->S)
4892 000,11110 00 1,0000 0,0 10000 n d FMOV Sd, Sn (not handled)
4897 UInt sD = dregNo(i->ARM64in.VUnaryS.dst);
4909 (b15 << 5) | X10000, sN, sD);
4913 000, 11110 00 1,001 11,1 10000 n d FRINTI Sd, Sm (round per FPCR)
4916 *p++ = X_3_8_5_6_5_5(X000, X11110001, X00111, X110000, sN, sD);
4951 UInt sD = dregNo(i->ARM64in.VBinS.dst);
4964 = X_3_8_5_6_5_5(X000, X11110001, sM, (b1512 << 2) | X10, sN, sD);
5271 011 01110 01 1 10000 001110 n d UADDLV Sd, Vn.8h
5275 010 01110 01 1 10000 001110 n d SADDLV Sd, Vn.8h
6413 /* 000 11110 00 10000 00 10000 n d FMOV Sd, Sn
