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Lines Matching refs:tR

448    HReg tR   = newVRegI(env);
451       tR = irrm >> 1;  if we're lucky, these will issue together
453       tR &= 1;         ditto
454       t3 = tL | tR;
462    addInstr(env, ARM64Instr_Shift(tR, irrm, ARM64RI6_I6(1), ARM64sh_SHR));
464    addInstr(env, ARM64Instr_Logic(tR, tR, ril_one, ARM64lo_AND));
465    addInstr(env, ARM64Instr_Logic(t3, tL, ARM64RIL_R(tR), ARM64lo_OR));