Lines Matching refs:HReg
49 /* The usual HReg abstraction.
53 void ppHRegARM ( HReg reg ) {
87 HReg hregARM_R0 ( void ) { return mkHReg(0, HRcInt32, False); }
88 HReg hregARM_R1 ( void ) { return mkHReg(1, HRcInt32, False); }
89 HReg hregARM_R2 ( void ) { return mkHReg(2, HRcInt32, False); }
90 HReg hregARM_R3 ( void ) { return mkHReg(3, HRcInt32, False); }
91 HReg hregARM_R4 ( void ) { return mkHReg(4, HRcInt32, False); }
92 HReg hregARM_R5 ( void ) { return mkHReg(5, HRcInt32, False); }
93 HReg hregARM_R6 ( void ) { return mkHReg(6, HRcInt32, False); }
94 HReg hregARM_R7 ( void ) { return mkHReg(7, HRcInt32, False); }
95 HReg hregARM_R8 ( void ) { return mkHReg(8, HRcInt32, False); }
96 HReg hregARM_R9 ( void ) { return mkHReg(9, HRcInt32, False); }
97 HReg hregARM_R10 ( void ) { return mkHReg(10, HRcInt32, False); }
98 HReg hregARM_R11 ( void ) { return mkHReg(11, HRcInt32, False); }
99 HReg hregARM_R12 ( void ) { return mkHReg(12, HRcInt32, False); }
100 HReg hregARM_R13 ( void ) { return mkHReg(13, HRcInt32, False); }
101 HReg hregARM_R14 ( void ) { return mkHReg(14, HRcInt32, False); }
102 HReg hregARM_R15 ( void ) { return mkHReg(15, HRcInt32, False); }
103 HReg hregARM_D8 ( void ) { return mkHReg(8, HRcFlt64, False); }
104 HReg hregARM_D9 ( void ) { return mkHReg(9, HRcFlt64, False); }
105 HReg hregARM_D10 ( void ) { return mkHReg(10, HRcFlt64, False); }
106 HReg hregARM_D11 ( void ) { return mkHReg(11, HRcFlt64, False); }
107 HReg hregARM_D12 ( void ) { return mkHReg(12, HRcFlt64, False); }
108 HReg hregARM_S26 ( void ) { return mkHReg(26, HRcFlt32, False); }
109 HReg hregARM_S27 ( void ) { return mkHReg(27, HRcFlt32, False); }
110 HReg hregARM_S28 ( void ) { return mkHReg(28, HRcFlt32, False); }
111 HReg hregARM_S29 ( void ) { return mkHReg(29, HRcFlt32, False); }
112 HReg hregARM_S30 ( void ) { return mkHReg(30, HRcFlt32, False); }
113 HReg hregARM_Q8 ( void ) { return mkHReg(8, HRcVec128, False); }
114 HReg hregARM_Q9 ( void ) { return mkHReg(9, HRcVec128, False); }
115 HReg hregARM_Q10 ( void ) { return mkHReg(10, HRcVec128, False); }
116 HReg hregARM_Q11 ( void ) { return mkHReg(11, HRcVec128, False); }
117 HReg hregARM_Q12 ( void ) { return mkHReg(12, HRcVec128, False); }
118 HReg hregARM_Q13 ( void ) { return mkHReg(13, HRcVec128, False); }
119 HReg hregARM_Q14 ( void ) { return mkHReg(14, HRcVec128, False); }
120 HReg hregARM_Q15 ( void ) { return mkHReg(15, HRcVec128, False); }
122 void getAllocableRegs_ARM ( Int* nregs, HReg** arr )
126 *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
219 ARMAMode1* ARMAMode1_RI ( HReg reg, Int simm13 ) {
227 ARMAMode1* ARMAMode1_RRS ( HReg base, HReg index, UInt shift ) {
287 ARMAMode2* ARMAMode2_RI ( HReg reg, Int simm9 ) {
295 ARMAMode2* ARMAMode2_RR ( HReg base, HReg index ) {
353 ARMAModeV* mkARMAModeV ( HReg reg, Int simm11 ) {
379 ARMAModeN *mkARMAModeN_RR ( HReg rN, HReg rM ) {
387 ARMAModeN *mkARMAModeN_R ( HReg rN ) {
446 ARMRI84* ARMRI84_R ( HReg reg ) {
501 ARMRI5* ARMRI5_R ( HReg reg ) {
660 ARMNRS* mkARMNRS(ARMNRS_tag tag, HReg reg, UInt index)
1101 HReg dst, HReg argL, ARMRI84* argR ) {
1111 HReg dst, HReg argL, ARMRI5* argR ) {
1120 ARMInstr* ARMInstr_Unary ( ARMUnaryOp op, HReg dst, HReg src ) {
1128 ARMInstr* ARMInstr_CmpOrTst ( Bool isCmp, HReg argL, ARMRI84* argR ) {
1136 ARMInstr* ARMInstr_Mov ( HReg dst, ARMRI84* src ) {
1143 ARMInstr* ARMInstr_Imm32 ( HReg dst, UInt imm32 ) {
1151 Bool isLoad, HReg rD, ARMAMode1* amode ) {
1163 HReg rD, ARMAMode2* amode ) {
1175 Bool isLoad, HReg rD, ARMAMode1* amode ) {
1185 ARMInstr* ARMInstr_Ld8S ( ARMCondCode cc, HReg rD, ARMAMode2* amode ) {
1204 ARMInstr* ARMInstr_XIndir ( HReg dstGA, ARMAMode1* amR15T,
1213 ARMInstr* ARMInstr_XAssisted ( HReg dstGA, ARMAMode1* amR15T,
1223 ARMInstr* ARMInstr_CMov ( ARMCondCode cond, HReg dst, ARMRI84* src ) {
1263 ARMInstr* ARMInstr_VLdStD ( Bool isLoad, HReg dD, ARMAModeV* am ) {
1271 ARMInstr* ARMInstr_VLdStS ( Bool isLoad, HReg fD, ARMAModeV* am ) {
1279 ARMInstr* ARMInstr_VAluD ( ARMVfpOp op, HReg dst, HReg argL, HReg argR ) {
1288 ARMInstr* ARMInstr_VAluS ( ARMVfpOp op, HReg dst, HReg argL, HReg argR ) {
1297 ARMInstr* ARMInstr_VUnaryD ( ARMVfpUnaryOp op, HReg dst, HReg src ) {
1305 ARMInstr* ARMInstr_VUnaryS ( ARMVfpUnaryOp op, HReg dst, HReg src ) {
1313 ARMInstr* ARMInstr_VCmpD ( HReg argL, HReg argR ) {
1320 ARMInstr* ARMInstr_VCMovD ( ARMCondCode cond, HReg dst, HReg src ) {
1329 ARMInstr* ARMInstr_VCMovS ( ARMCondCode cond, HReg dst, HReg src ) {
1338 ARMInstr* ARMInstr_VCvtSD ( Bool sToD, HReg dst, HReg src ) {
1346 ARMInstr* ARMInstr_VXferD ( Bool toD, HReg dD, HReg rHi, HReg rLo ) {
1355 ARMInstr* ARMInstr_VXferS ( Bool toS, HReg fD, HReg rLo ) {
1364 HReg dst, HReg src ) {
1373 ARMInstr* ARMInstr_FPSCR ( Bool toFPSCR, HReg iReg ) {
1391 ARMInstr* ARMInstr_NLdStQ ( Bool isLoad, HReg dQ, ARMAModeN *amode ) {
1400 ARMInstr* ARMInstr_NLdStD ( Bool isLoad, HReg dD, ARMAModeN *amode ) {
1409 ARMInstr* ARMInstr_NUnary ( ARMNeonUnOp op, HReg dQ, HReg nQ,
1433 ARMInstr* ARMInstr_NDual ( ARMNeonDualOp op, HReg nQ, HReg mQ,
1446 HReg dst, HReg argL, HReg argR,
1459 ARMInstr* ARMInstr_NeonImm (HReg dst, ARMNImm* imm ) {
1467 ARMInstr* ARMInstr_NCMovQ ( ARMCondCode cond, HReg dst, HReg src ) {
1478 HReg dst, HReg argL, HReg argR,
1491 ARMInstr* ARMInstr_NShl64 ( HReg dst, HReg src, UInt amt )
1518 ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) {
2526 Bool isMove_ARMInstr ( ARMInstr* i, HReg* src, HReg* dst )
2571 HReg rreg, Int offsetB, Bool mode64 )
2588 HReg r8 = hregARM_R8(); /* baseblock */
2589 HReg r12 = hregARM_R12(); /* spill temp */
2590 HReg base = r8;
2613 HReg r8 = hregARM_R8();
2614 HReg r12 = hregARM_R12();
2626 HReg rreg, Int offsetB, Bool mode64 )
2643 HReg r8 = hregARM_R8(); /* baseblock */
2644 HReg r12 = hregARM_R12(); /* spill temp */
2645 HReg base = r8;
2668 HReg r8 = hregARM_R8();
2669 HReg r12 = hregARM_R12();
2685 static inline UChar iregNo ( HReg r )
2695 static inline UChar dregNo ( HReg r )
2707 static inline UChar fregNo ( HReg r )
2717 static inline UChar qregNo ( HReg r )
3086 HReg rD;
3126 HReg rD = i->ARMin.LdSt16.rD;
3133 HReg rN = am->ARMam2.RI.reg;
3175 HReg rD = i->ARMin.Ld8S.rD;
3180 HReg rN = am->ARMam2.RI.reg;
4526 HReg regDreg = i->ARMin.NShl64.dst;
4527 HReg regMreg = i->ARMin.NShl64.src;
