Lines Matching refs:nArgRegs
1232 ARMInstr* ARMInstr_Call ( ARMCondCode cond, HWord target, Int nArgRegs,
1238 i->ARMin.Call.nArgRegs = nArgRegs;
1703 vex_printf("0x%lx [nArgRegs=%d, ",
1704 i->ARMin.Call.target, i->ARMin.Call.nArgRegs);
2121 which might be read. This depends on nArgRegs. */
2122 switch (i->ARMin.Call.nArgRegs) {
2132 loaded into a register. Fortunately, for the nArgRegs=
2135 nArgRegs=4 case, we'll have to choose another register
2139 if (i->ARMin.Call.nArgRegs == 4)
2143 address temporary, depending on nArgRegs: 0==r0,
3390 switch (i->ARMin.Call.nArgRegs) {
