Lines Matching refs:rD
1151 Bool isLoad, HReg rD, ARMAMode1* amode ) {
1156 i->ARMin.LdSt32.rD = rD;
1163 HReg rD, ARMAMode2* amode ) {
1169 i->ARMin.LdSt16.rD = rD;
1175 Bool isLoad, HReg rD, ARMAMode1* amode ) {
1180 i->ARMin.LdSt8U.rD = rD;
1185 ARMInstr* ARMInstr_Ld8S ( ARMCondCode cc, HReg rD, ARMAMode2* amode ) {
1189 i->ARMin.Ld8S.rD = rD;
1518 ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) {
1525 i->ARMin.Alu.dst = rD;
1530 i->ARMin.Add32.rD = rD;
1599 ppHRegARM(i->ARMin.LdSt32.rD);
1607 ppHRegARM(i->ARMin.LdSt32.rD);
1617 ppHRegARM(i->ARMin.LdSt16.rD);
1626 ppHRegARM(i->ARMin.LdSt16.rD);
1633 ppHRegARM(i->ARMin.LdSt8U.rD);
1641 ppHRegARM(i->ARMin.LdSt8U.rD);
1649 ppHRegARM(i->ARMin.Ld8S.rD);
1986 ppHRegARM(i->ARMin.Add32.rD);
2054 addHRegUse(u, HRmWrite, i->ARMin.LdSt32.rD);
2056 addHRegUse(u, HRmRead, i->ARMin.LdSt32.rD);
2058 addHRegUse(u, HRmRead, i->ARMin.LdSt32.rD);
2064 addHRegUse(u, HRmWrite, i->ARMin.LdSt16.rD);
2066 addHRegUse(u, HRmRead, i->ARMin.LdSt16.rD);
2068 addHRegUse(u, HRmRead, i->ARMin.LdSt16.rD);
2074 addHRegUse(u, HRmWrite, i->ARMin.LdSt8U.rD);
2076 addHRegUse(u, HRmRead, i->ARMin.LdSt8U.rD);
2078 addHRegUse(u, HRmRead, i->ARMin.LdSt8U.rD);
2083 addHRegUse(u, HRmWrite, i->ARMin.Ld8S.rD);
2085 addHRegUse(u, HRmRead, i->ARMin.Ld8S.rD);
2305 addHRegUse(u, HRmWrite, i->ARMin.Add32.rD);
2357 i->ARMin.LdSt32.rD = lookupHRegRemap(m, i->ARMin.LdSt32.rD);
2361 i->ARMin.LdSt16.rD = lookupHRegRemap(m, i->ARMin.LdSt16.rD);
2365 i->ARMin.LdSt8U.rD = lookupHRegRemap(m, i->ARMin.LdSt8U.rD);
2369 i->ARMin.Ld8S.rD = lookupHRegRemap(m, i->ARMin.Ld8S.rD);
2503 i->ARMin.Add32.rD = lookupHRegRemap(m, i->ARMin.Add32.rD);
2815 static UInt* imm32_to_iregNo ( UInt* p, Int rD, UInt imm32 )
2818 vassert(rD >= 0 && rD <= 14); // r15 not good to mess with!
2822 instr = XXXXXX__(X1110,X0011,X1010,X0000,rD,X0000);
2827 // ldr rD, [pc]
2828 instr = XXXXX___(X1110,X0101,X1001,X1111,rD);
2838 /* Generate movw rD, #low16. Then, if the high 16 are
2839 nonzero, generate movt rD, #high16. */
2842 instr = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
2847 instr = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
2859 instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
2862 rN = rD;
2867 instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
2870 rN = rD;
2875 instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
2878 rN = rD;
2883 instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
2886 rN = rD;
2897 static UInt* imm32_to_iregNo_EXACTLY2 ( UInt* p, Int rD, UInt imm32 )
2900 /* Generate movw rD, #low16 ; movt rD, #high16. */
2904 instr = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
2908 instr = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
2920 static Bool is_imm32_to_iregNo_EXACTLY2 ( UInt* p, Int rD, UInt imm32 )
2923 /* Generate movw rD, #low16 ; movt rD, #high16. */
2927 i0 = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
2930 i1 = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
2941 Bool isLoad, UInt rD, ARMAMode1* am )
2943 vassert(rD <= 12);
2959 rD);
2988 UInt rD = iregNo(i->ARMin.Alu.dst);
3006 (subopc << 1) & 0xF, rN, rD);
3016 UInt rD = iregNo(i->ARMin.Shift.dst);
3026 instr |= XXXXX__X(X1110,X0001,X1010,X0000,rD, /* _ _ */ rM);
3041 case ARMun_NEG: /* RSB rD,rS,#0 */
3086 HReg rD;
3093 rD = i->ARMin.LdSt32.rD;
3099 rD = i->ARMin.LdSt8U.rD;
3116 iregNo(rD));
3126 HReg rD = i->ARMin.LdSt16.rD;
3150 iregNo(rD), imm8hi, X1011, imm8lo);
3157 iregNo(rD), imm8hi, X1011, imm8lo);
3164 iregNo(rD), imm8hi, X1111, imm8lo);
3175 HReg rD = i->ARMin.Ld8S.rD;
3195 iregNo(rD), imm8hi, X1101, imm8lo);
4612 UInt regD = iregNo(i->ARMin.Add32.rD);
