Lines Matching full:imm32
29 ###adcl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999]
30 ###adcl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000]
31 adcl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[99999999]
32 adcl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[100000000]
33 adcl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999]
34 adcl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[100000000]
43 ###adcq eflags[0x1,0x0] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432199999999]
44 ###adcq eflags[0x1,0x1] : imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432200000000]
45 adcq eflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432199999999]
46 adcq eflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432200000000]
47 adcq eflags[0x1,0x0] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432199999999]
48 adcq eflags[0x1,0x1] : imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432200000000]
69 addl imm32[12345678] eax.ud[87654321] => 1.ud[99999999]
70 addl imm32[12345678] ebx.ud[87654321] => 1.ud[99999999]
71 addl imm32[12345678] m32.ud[87654321] => 1.ud[99999999]
76 addq imm32[12345678] rax.uq[8765432187654321] => 1.uq[8765432199999999]
77 addq imm32[12345678] rbx.uq[8765432187654321] => 1.uq[8765432199999999]
78 addq imm32[12345678] m64.uq[8765432187654321] => 1.uq[8765432199999999]
96 andl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x02005430]
97 andl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x02005430]
98 andl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x02005430]
103 andq imm32[0x12345678] rax.uq[0x8642753186427531] => 1.uq[0x0000000002005430]
104 andq imm32[0x12345678] rbx.uq[0x8642753186427531] => 1.uq[0x0000000002005430]
105 andq imm32[0x12345678] m64.uq[0x8642753186427531] => 1.uq[0x0000000002005430]
106 andq imm32[-2042464975] rax.uq[0x1234567812345678] => 1.uq[0x1234567802005430]
107 andq imm32[-2042464975] rbx.uq[0x1234567812345678] => 1.uq[0x1234567802005430]
108 andq imm32[-2042464975] m64.uq[0x1234567812345678] => 1.uq[0x1234567802005430]
394 cmpl imm32[3] eax.ud[2] => eflags[0x010,0x010]
395 cmpl imm32[2] eax.ud[3] => eflags[0x010,0x000]
396 cmpl imm32[12] eax.ud[12] => eflags[0x044,0x044]
397 cmpl imm32[12] eax.ud[34] => eflags[0x044,0x000]
398 cmpl imm32[34] eax.ud[12] => eflags[0x081,0x081]
399 cmpl imm32[12] eax.ud[34] => eflags[0x081,0x000]
400 cmpl imm32[100] eax.sd[-2147483600] => eflags[0x800,0x800]
401 cmpl imm32[50] eax.sd[-50] => eflags[0x800,0x000]
402 cmpl imm32[-50] eax.sd[50] => eflags[0x800,0x000]
403 cmpl imm32[-100] eax.sd[2147483600] => eflags[0x800,0x800]
404 cmpl imm32[3] r32.ud[2] => eflags[0x010,0x010]
405 cmpl imm32[2] r32.ud[3] => eflags[0x010,0x000]
406 cmpl imm32[12] r32.ud[12] => eflags[0x044,0x044]
407 cmpl imm32[12] r32.ud[34] => eflags[0x044,0x000]
408 cmpl imm32[34] r32.ud[12] => eflags[0x081,0x081]
409 cmpl imm32[12] r32.ud[34] => eflags[0x081,0x000]
410 cmpl imm32[100] r32.sd[-2147483600] => eflags[0x800,0x800]
411 cmpl imm32[50] r32.sd[-50] => eflags[0x800,0x000]
412 cmpl imm32[-50] r32.sd[50] => eflags[0x800,0x000]
413 cmpl imm32[-100] r32.sd[2147483600] => eflags[0x800,0x800]
414 cmpl imm32[3] m32.ud[2] => eflags[0x010,0x010]
415 cmpl imm32[2] m32.ud[3] => eflags[0x010,0x000]
416 cmpl imm32[12] m32.ud[12] => eflags[0x044,0x044]
417 cmpl imm32[12] m32.ud[34] => eflags[0x044,0x000]
418 cmpl imm32[34] m32.ud[12] => eflags[0x081,0x081]
419 cmpl imm32[12] m32.ud[34] => eflags[0x081,0x000]
420 cmpl imm32[100] m32.sd[-2147483600] => eflags[0x800,0x800]
421 cmpl imm32[50] m32.sd[-50] => eflags[0x800,0x000]
422 cmpl imm32[-50] m32.sd[50] => eflags[0x800,0x000]
423 cmpl imm32[-100] m32.sd[2147483600] => eflags[0x800,0x800]
474 cmpq imm32[3] rax.uq[2] => eflags[0x010,0x010]
475 cmpq imm32[2] rax.uq[3] => eflags[0x010,0x000]
476 cmpq imm32[12] rax.uq[12] => eflags[0x044,0x044]
477 cmpq imm32[12] rax.uq[34] => eflags[0x044,0x000]
478 cmpq imm32[34] rax.uq[12] => eflags[0x081,0x081]
479 cmpq imm32[12] rax.uq[34] => eflags[0x081,0x000]
480 cmpq imm32[100] rax.sq[-9223372036854775800] => eflags[0x800,0x800]
481 cmpq imm32[50] rax.sq[-50] => eflags[0x800,0x000]
482 cmpq imm32[-50] rax.sq[50] => eflags[0x800,0x000]
483 cmpq imm32[-100] rax.sq[9223372036854775800] => eflags[0x800,0x800]
484 cmpq imm32[3] r64.uq[2] => eflags[0x010,0x010]
485 cmpq imm32[2] r64.uq[3] => eflags[0x010,0x000]
486 cmpq imm32[12] r64.uq[12] => eflags[0x044,0x044]
487 cmpq imm32[12] r64.uq[34] => eflags[0x044,0x000]
488 cmpq imm32[34] r64.uq[12] => eflags[0x081,0x081]
489 cmpq imm32[12] r64.uq[34] => eflags[0x081,0x000]
490 cmpq imm32[100] r64.sq[-9223372036854775800] => eflags[0x800,0x800]
491 cmpq imm32[50] r64.sq[-50] => eflags[0x800,0x000]
492 cmpq imm32[-50] r64.sq[50] => eflags[0x800,0x000]
493 cmpq imm32[-100] r64.sq[9223372036854775800] => eflags[0x800,0x800]
494 cmpq imm32[3] m64.uq[2] => eflags[0x010,0x010]
495 cmpq imm32[2] m64.uq[3] => eflags[0x010,0x000]
496 cmpq imm32[12] m64.uq[12] => eflags[0x044,0x044]
497 cmpq imm32[12] m64.uq[34] => eflags[0x044,0x000]
498 cmpq imm32[34] m64.uq[12] => eflags[0x081,0x081]
499 cmpq imm32[12] m64.uq[34] => eflags[0x081,0x000]
500 cmpq imm32[100] m64.sq[-9223372036854775800] => eflags[0x800,0x800]
501 cmpq imm32[50] m64.sq[-50] => eflags[0x800,0x000]
502 cmpq imm32[-50] m64.sq[50] => eflags[0x800,0x000]
503 cmpq imm32[-100] m64.sq[9223372036854775800] => eflags[0x800,0x800]
599 imull imm32[12345] r32.ud[67890] => 1.ud[838102050]
600 imull imm32[12345] r32.ud[67890] r32.ud[0] => 2.ud[838102050]
601 imull imm32[12345] m32.ud[67890] r32.ud[0] => 2.ud[838102050]
607 imulq imm32[12345] r64.uq[1234567890] => 1.uq[15240740602050]
608 imulq imm32[12345] r64.uq[1234567890] r64.uq[0] => 2.uq[15240740602050]
609 imulq imm32[12345] m64.uq[1234567890] r64.uq[0] => 2.uq[15240740602050]
632 movl imm32[12345678] r32.ud[0] => 1.ud[12345678]
633 movl imm32[12345678] m32.ud[0] => 1.ud[12345678]
637 movq imm32[12345678] r64.uq[0] => 1.uq[12345678]
638 movq imm32[12345678] m64.uq[0] => 1.uq[12345678]
701 orl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x96767779]
702 orl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x96767779]
703 orl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x96767779]
708 orq imm32[0x12345678] rax.uq[0x8642753186427531] => 1.uq[0x8642753196767779]
709 orq imm32[0x12345678] rbx.uq[0x8642753186427531] => 1.uq[0x8642753196767779]
710 orq imm32[0x12345678] m64.uq[0x8642753186427531] => 1.uq[0x8642753196767779]
711 orq imm32[-2042464975] rax.uq[0x1234567812345678] => 1.uq[0xffffffff96767779]
712 orq imm32[-2042464975] rbx.uq[0x1234567812345678] => 1.uq[0xffffffff96767779]
713 orq imm32[-2042464975] m64.uq[0x1234567812345678] => 1.uq[0xffffffff96767779]
891 ###sbbl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643]
892 ###sbbl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642]
893 sbbl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308643]
894 sbbl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308642]
895 sbbl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643]
896 sbbl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[75308642]
905 ###sbbq eflags[0x1,0x0] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972964]
906 ###sbbq eflags[0x1,0x1] : imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972963]
907 sbbq eflags[0x1,0x0] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972964]
908 sbbq eflags[0x1,0x1] : imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972963]
909 sbbq eflags[0x1,0x0] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972964]
910 sbbq eflags[0x1,0x1] : imm32[12345678] m64.uq[8765432175318642] => 1.uq[8765432162972963]
1223 subl imm32[12345678] r32.ud[87654321] => 1.ud[75308643]
1224 subl imm32[12345678] eax.ud[87654321] => 1.ud[75308643]
1225 subl imm32[12345678] ebx.ud[87654321] => 1.ud[75308643]
1230 subq imm32[12345678] r64.uq[8765432175318642] => 1.uq[8765432162972964]
1231 subq imm32[12345678] rax.uq[8765432175318642] => 1.uq[8765432162972964]
1232 subq imm32[12345678] rbx.uq[8765432175318642] => 1.uq[8765432162972964]
1286 testl imm32[0x1a1a1a1a] eax.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
1287 testl imm32[0x5a5a5a5a] eax.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
1288 testl imm32[0x1a1a1a1a] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
1289 testl imm32[0xa1a1a1a1] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
1290 testl imm32[0xa5a5a5a5] eax.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
1291 testl imm32[0x1a1a1a1a] ebx.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
1292 testl imm32[0x5a5a5a5a] ebx.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
1293 testl imm32[0x1a1a1a1a] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
1294 testl imm32[0xa1a1a1a1] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
1295 testl imm32[0xa5a5a5a5] ebx.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
1296 testl imm32[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
1297 testl imm32[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
1298 testl imm32[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
1299 testl imm32[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
1300 testl imm32[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
1311 testq imm32[0x1a1a1a1a] rax.uq[0x1a1a1a1a] => eflags[0x8c5,0x000]
1312 testq imm32[0x5a5a5a5a] rax.uq[0x5a5a5a5a] => eflags[0x8c5,0x004]
1313 testq imm32[0x1a1a1a1a] rax.uq[0xa1a1a1a1] => eflags[0x8c5,0x044]
1314 testq imm32[-1583242847] rax.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080]
1315 testq imm32[-1515870811] rax.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084]
1316 testq imm32[0x1a1a1a1a] rbx.uq[0x1a1a1a1a] => eflags[0x8c5,0x000]
1317 testq imm32[0x5a5a5a5a] rbx.uq[0x5a5a5a5a] => eflags[0x8c5,0x004]
1318 testq imm32[0x1a1a1a1a] rbx.uq[0xa1a1a1a1] => eflags[0x8c5,0x044]
1319 testq imm32[-1583242847] rbx.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080]
1320 testq imm32[-1515870811] rbx.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084]
1321 testq imm32[0x1a1a1a1a] m64.uq[0x1a1a1a1a] => eflags[0x8c5,0x000]
1322 testq imm32[0x5a5a5a5a] m64.uq[0x5a5a5a5a] => eflags[0x8c5,0x004]
1323 testq imm32[0x1a1a1a1a] m64.uq[0xa1a1a1a1] => eflags[0x8c5,0x044]
1324 testq imm32[-1583242847] m64.uq[0xffffffffa1a1a1a1] => eflags[0x8c5,0x080]
1325 testq imm32[-1515870811] m64.uq[0xffffffffa5a5a5a5] => eflags[0x8c5,0x084]
1376 xorl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x94762349]
1377 xorl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x94762349]
1378 xorl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x94762349]
1383 xorq imm32[0x12345678] rax.uq[0x8642753186427531] => 1.uq[0x8642753194762349]
1384 xorq imm32[0x12345678] rbx.uq[0x8642753186427531] => 1.uq[0x8642753194762349]
1385 xorq imm32[0x12345678] m64.uq[0x8642753186427531] => 1.uq[0x8642753194762349]
1386 xorq imm32[-2042464975] rax.uq[0x1234567812345678] => 1.uq[0xedcba98794762349]
1387 imm32[-2042464975] rbx.uq[0x1234567812345678] => 1.uq[0xedcba98794762349]
1388 xorq imm32[-2042464975] m64.uq[0x1234567812345678] => 1.uq[0xedcba98794762349]
