Home | History | Annotate | Download | only in a64

Lines Matching refs:Ra

875                      const Register& ra,
877 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
892 const Register& ra) {
893 DataProcessing3Source(rd, rn, rm, ra, MADD);
908 const Register& ra) {
909 DataProcessing3Source(rd, rn, rm, ra, MSUB);
916 const Register& ra) {
917 VIXL_ASSERT(rd.Is64Bits() && ra.Is64Bits());
919 DataProcessing3Source(rd, rn, rm, ra, UMADDL_x);
926 const Register& ra) {
927 VIXL_ASSERT(rd.Is64Bits() && ra.Is64Bits());
929 DataProcessing3Source(rd, rn, rm, ra, SMADDL_x);
936 const Register& ra) {
937 VIXL_ASSERT(rd.Is64Bits() && ra.Is64Bits());
939 DataProcessing3Source(rd, rn, rm, ra, UMSUBL_x);
946 const Register& ra) {
947 VIXL_ASSERT(rd.Is64Bits() && ra.Is64Bits());
949 DataProcessing3Source(rd, rn, rm, ra, SMSUBL_x);
1743 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd) | Ra(fa));