Lines Matching refs:Rm
702 const Register& rm) {
704 VIXL_ASSERT(rd.size() == rm.size());
705 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
711 const Register& rm) {
713 VIXL_ASSERT(rd.size() == rm.size());
714 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
720 const Register& rm) {
722 VIXL_ASSERT(rd.size() == rm.size());
723 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd));
729 const Register& rm) {
731 VIXL_ASSERT(rd.size() == rm.size());
732 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd));
772 const Register& rm,
775 VIXL_ASSERT(rd.size() == rm.size());
777 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.size()) | Rn(rn) | Rd(rd));
783 const Register& rm,
785 ConditionalSelect(rd, rn, rm, cond, CSEL);
791 const Register& rm,
793 ConditionalSelect(rd, rn, rm, cond, CSINC);
799 const Register& rm,
801 ConditionalSelect(rd, rn, rm, cond, CSINV);
807 const Register& rm,
809 ConditionalSelect(rd, rn, rm, cond, CSNEG);
847 const Register& rm,
851 VIXL_ASSERT(rd.size() == rm.size());
852 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd));
874 const Register& rm,
877 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
883 const Register& rm) {
884 VIXL_ASSERT(AreSameSizeAndType(rd, rn, rm));
885 DataProcessing3Source(rd, rn, rm, AppropriateZeroRegFor(rd), MADD);
891 const Register& rm,
893 DataProcessing3Source(rd, rn, rm, ra, MADD);
899 const Register& rm) {
900 VIXL_ASSERT(AreSameSizeAndType(rd, rn, rm));
901 DataProcessing3Source(rd, rn, rm, AppropriateZeroRegFor(rd), MSUB);
907 const Register& rm,
909 DataProcessing3Source(rd, rn, rm, ra, MSUB);
915 const Register& rm,
918 VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
919 DataProcessing3Source(rd, rn, rm, ra, UMADDL_x);
925 const Register& rm,
928 VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
929 DataProcessing3Source(rd, rn, rm, ra, SMADDL_x);
935 const Register& rm,
938 VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
939 DataProcessing3Source(rd, rn, rm, ra, UMSUBL_x);
945 const Register& rm,
948 VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
949 DataProcessing3Source(rd, rn, rm, ra, SMSUBL_x);
955 const Register& rm) {
957 VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
958 DataProcessing3Source(rd, rn, rm, xzr, SMADDL_x);
964 const Register& rm) {
966 VIXL_ASSERT(rd.size() == rm.size());
967 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd));
980 const Register& rm) {
982 VIXL_ASSERT(rd.size() == rm.size());
983 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd));
1168 void Assembler::mov(const Register& rd, const Register& rm) {
1172 if (rd.IsSP() || rm.IsSP()) {
1173 add(rd, rm, 0);
1175 orr(rd, AppropriateZeroRegFor(rd), rm);
1391 Emit(FPType(fn) | FCMP | Rm(fm) | Rn(fn));
1411 Emit(FPType(fn) | FCCMP | Rm(fm) | Cond(cond) | Rn(fn) | Nzcv(nzcv));
1421 Emit(FPType(fd) | FCSEL | Rm(fm) | Cond(cond) | Rn(fn) | Rd(fd));
1628 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd));
1706 ccmpop = ConditionalCompareRegisterFixed | op | Rm(operand.reg());
1733 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd));
1743 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd) | Ra(fa));
1817 Rm(operand.reg()) | Rn(rn) | Rd(rd));
1827 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) |
1871 Emit(LoadStoreRegisterOffsetFixed | memop | Rm(addr.regoffset()) |
