Lines Matching refs:Rn
433 Emit(BR | Rn(xn));
439 Emit(BLR | Rn(xn));
445 Emit(RET | Rn(xn));
545 const Register& rn,
547 AddSub(rd, rn, operand, LeaveFlags, ADD);
552 const Register& rn,
554 AddSub(rd, rn, operand, SetFlags, ADD);
558 void Assembler::cmn(const Register& rn,
560 Register zr = AppropriateZeroRegFor(rn);
561 adds(zr, rn, operand);
566 const Register& rn,
568 AddSub(rd, rn, operand, LeaveFlags, SUB);
573 const Register& rn,
575 AddSub(rd, rn, operand, SetFlags, SUB);
579 void Assembler::cmp(const Register& rn, const Operand& operand) {
580 Register zr = AppropriateZeroRegFor(rn);
581 subs(zr, rn, operand);
598 const Register& rn,
600 AddSubWithCarry(rd, rn, operand, LeaveFlags, ADC);
605 const Register& rn,
607 AddSubWithCarry(rd, rn, operand, SetFlags, ADC);
612 const Register& rn,
614 AddSubWithCarry(rd, rn, operand, LeaveFlags, SBC);
619 const Register& rn,
621 AddSubWithCarry(rd, rn, operand, SetFlags, SBC);
639 const Register& rn,
641 Logical(rd, rn, operand, AND);
646 const Register& rn,
648 Logical(rd, rn, operand, ANDS);
652 void Assembler::tst(const Register& rn,
654 ands(AppropriateZeroRegFor(rn), rn, operand);
659 const Register& rn,
661 Logical(rd, rn, operand, BIC);
666 const Register& rn,
668 Logical(rd, rn, operand, BICS);
673 const Register& rn,
675 Logical(rd, rn, operand, ORR);
680 const Register& rn,
682 Logical(rd, rn, operand, ORN);
687 const Register& rn,
689 Logical(rd, rn, operand, EOR);
694 const Register& rn,
696 Logical(rd, rn, operand, EON);
701 const Register& rn,
703 VIXL_ASSERT(rd.size() == rn.size());
705 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
710 const Register& rn,
712 VIXL_ASSERT(rd.size() == rn.size());
714 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
719 const Register& rn,
721 VIXL_ASSERT(rd.size() == rn.size());
723 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd));
728 const Register& rn,
730 VIXL_ASSERT(rd.size() == rn.size());
732 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd));
738 const Register& rn,
741 VIXL_ASSERT(rd.size() == rn.size());
744 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
749 const Register& rn,
752 VIXL_ASSERT(rd.Is64Bits() || rn.Is32Bits());
755 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
760 const Register& rn,
763 VIXL_ASSERT(rd.size() == rn.size());
766 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
771 const Register& rn,
774 VIXL_ASSERT(rd.size() == rn.size());
777 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.size()) | Rn(rn) | Rd(rd));
782 const Register& rn,
785 ConditionalSelect(rd, rn, rm, cond, CSEL);
790 const Register& rn,
793 ConditionalSelect(rd, rn, rm, cond, CSINC);
798 const Register& rn,
801 ConditionalSelect(rd, rn, rm, cond, CSINV);
806 const Register& rn,
809 ConditionalSelect(rd, rn, rm, cond, CSNEG);
827 void Assembler::cinc(const Register &rd, const Register &rn, Condition cond) {
829 csinc(rd, rn, rn, InvertCondition(cond));
833 void Assembler::cinv(const Register &rd, const Register &rn, Condition cond) {
835 csinv(rd, rn, rn, InvertCondition(cond));
839 void Assembler::cneg(const Register &rd, const Register &rn, Condition cond) {
841 csneg(rd, rn, rn, InvertCondition(cond));
846 const Register& rn,
850 VIXL_ASSERT(rd.size() == rn.size());
852 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd));
856 void Assembler::ccmn(const Register& rn,
860 ConditionalCompare(rn, operand, nzcv, cond, CCMN);
864 void Assembler::ccmp(const Register& rn,
868 ConditionalCompare(rn, operand, nzcv, cond, CCMP);
873 const Register& rn,
877 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
882 const Register& rn,
884 VIXL_ASSERT(AreSameSizeAndType(rd, rn, rm));
885 DataProcessing3Source(rd, rn, rm, AppropriateZeroRegFor(rd), MADD);
890 const Register& rn,
893 DataProcessing3Source(rd, rn, rm, ra, MADD);
898 const Register& rn,
900 VIXL_ASSERT(AreSameSizeAndType(rd, rn, rm));
901 DataProcessing3Source(rd, rn, rm, AppropriateZeroRegFor(rd), MSUB);
906 const Register& rn,
909 DataProcessing3Source(rd, rn, rm, ra, MSUB);
914 const Register& rn,
918 VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
919 DataProcessing3Source(rd, rn, rm, ra, UMADDL_x);
924 const Register& rn,
928 VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
929 DataProcessing3Source(rd, rn, rm, ra, SMADDL_x);
934 const Register& rn,
938 VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
939 DataProcessing3Source(rd, rn, rm, ra, UMSUBL_x);
944 const Register& rn,
948 VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
949 DataProcessing3Source(rd, rn, rm, ra, SMSUBL_x);
954 const Register& rn,
957 VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
958 DataProcessing3Source(rd, rn, rm, xzr, SMADDL_x);
963 const Register& rn,
965 VIXL_ASSERT(rd.size() == rn.size());
967 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd));
979 const Register& rn,
981 VIXL_ASSERT(rd.size() == rn.size());
983 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd));
988 const Register& rn) {
989 DataProcessing1Source(rd, rn, RBIT);
994 const Register& rn) {
995 DataProcessing1Source(rd, rn, REV16);
1000 const Register& rn) {
1002 DataProcessing1Source(rd, rn, REV);
1007 const Register& rn) {
1008 DataProcessing1Source(rd, rn, rd.Is64Bits() ? REV_x : REV_w);
1013 const Register& rn) {
1014 DataProcessing1Source(rd, rn, CLZ);
1019 const Register& rn) {
1020 DataProcessing1Source(rd, rn, CLS);
1234 Emit(op | Rd(rd) | Rn(fn));
1238 void Assembler::fmov(const FPRegister& fd, const Register& rn) {
1239 VIXL_ASSERT(fd.size() == rn.size());
1241 Emit(op | Rd(fd) | Rn(rn));
1247 Emit(FPType(fd) | FMOV | Rd(fd) | Rn(fn));
1391 Emit(FPType(fn) | FCMP | Rm(fm) | Rn(fn));
1402 Emit(FPType(fn) | FCMP_zero | Rn(fn));
1411 Emit(FPType(fn) | FCCMP | Rm(fm) | Cond(cond) | Rn(fn) | Nzcv(nzcv));
1421 Emit(FPType(fd) | FCSEL | Rm(fm) | Cond(cond) | Rn(fn) | Rd(fd));
1428 Emit(SF(rd) | FPType(fn) | op | Rn(fn) | Rd(rd));
1487 const Register& rn,
1490 Emit(SF(rn) | FPType(fd) | SCVTF | Rn(rn) | Rd(fd));
1492 Emit(SF(rn) | FPType(fd) | SCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
1499 const Register& rn,
1502 Emit(SF(rn) | FPType(fd) | UCVTF | Rn(rn) | Rd(fd));
1504 Emit(SF(rn) | FPType(fd) | UCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
1584 const Register& rn,
1588 VIXL_ASSERT(rd.size() == rn.size());
1594 ImmAddSub(immediate) | dest_reg | RnSP(rn));
1606 if (rn.IsSP() || rd.IsSP()) {
1608 DataProcExtendedRegister(rd, rn, operand.ToExtendedRegister(), S,
1611 DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op);
1615 DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op);
1621 const Register& rn,
1625 VIXL_ASSERT(rd.size() == rn.size());
1628 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd));
1645 const Register& rn,
1648 VIXL_ASSERT(rd.size() == rn.size());
1666 LogicalImmediate(rd, rn, n, imm_s, imm_r, op);
1675 DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op);
1681 const Register& rn,
1690 Rn(rn));
1694 void Assembler::ConditionalCompare(const Register& rn,
1708 Emit(SF(rn) | ccmpop | Cond(cond) | Rn(rn) | Nzcv(nzcv));
1713 const Register& rn,
1715 VIXL_ASSERT(rd.size() == rn.size());
1716 Emit(SF(rn) | op | Rn(rn) | Rd(rd));
1723 Emit(FPType(fn) | op | Rn(fn) | Rd(fd));
1733 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd));
1743 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd) | Ra(fa));
1748 const Register& rn,
1753 lsl(rd, rn, shift_amount);
1756 lsr(rd, rn, shift_amount);
1759 asr(rd, rn, shift_amount);
1762 ror(rd, rn, shift_amount);
1771 const Register& rn,
1774 VIXL_ASSERT(rd.size() >= rn.size());
1777 Register rn_ = Register(rn.code(), rd.size());
1793 VIXL_ASSERT(rn.size() == kXRegSize);
1808 const Register& rn,
1813 VIXL_ASSERT(rn.Is64Bits() || (rn.Is32Bits() &&
1817 Rm(operand.reg()) | Rn(rn) | Rd(rd));
1822 const Register& rn,
1829 dest_reg | RnSP(rn));
