Lines Matching refs:Rn
739 const Register& rn,
744 const Register& rn,
748 void cmn(const Register& rn, const Operand& operand);
752 const Register& rn,
757 const Register& rn,
761 void cmp(const Register& rn, const Operand& operand);
773 const Register& rn,
778 const Register& rn,
783 const Register& rn,
788 const Register& rn,
802 const Register& rn,
807 const Register& rn,
811 void tst(const Register& rn, const Operand& operand);
815 const Register& rn,
820 const Register& rn,
824 void orr(const Register& rd, const Register& rn, const Operand& operand);
827 void orn(const Register& rd, const Register& rn, const Operand& operand);
830 void eor(const Register& rd, const Register& rn, const Operand& operand);
833 void eon(const Register& rd, const Register& rn, const Operand& operand);
836 void lslv(const Register& rd, const Register& rn, const Register& rm);
839 void lsrv(const Register& rd, const Register& rn, const Register& rm);
842 void asrv(const Register& rd, const Register& rn, const Register& rm);
845 void rorv(const Register& rd, const Register& rn, const Register& rm);
850 const Register& rn,
856 const Register& rn,
862 const Register& rn,
869 const Register& rn,
873 VIXL_ASSERT(lsb + width <= rn.size());
874 bfm(rd, rn, (rd.size() - lsb) & (rd.size() - 1), width - 1);
879 const Register& rn,
883 VIXL_ASSERT(lsb + width <= rn.size());
884 bfm(rd, rn, lsb, lsb + width - 1);
889 inline void asr(const Register& rd, const Register& rn, unsigned shift) {
891 sbfm(rd, rn, shift, rd.size() - 1);
896 const Register& rn,
900 VIXL_ASSERT(lsb + width <= rn.size());
901 sbfm(rd, rn, (rd.size() - lsb) & (rd.size() - 1), width - 1);
906 const Register& rn,
910 VIXL_ASSERT(lsb + width <= rn.size());
911 sbfm(rd, rn, lsb, lsb + width - 1);
915 inline void sxtb(const Register& rd, const Register& rn) {
916 sbfm(rd, rn, 0, 7);
920 inline void sxth(const Register& rd, const Register& rn) {
921 sbfm(rd, rn, 0, 15);
925 inline void sxtw(const Register& rd, const Register& rn) {
926 sbfm(rd, rn, 0, 31);
931 inline void lsl(const Register& rd, const Register& rn, unsigned shift) {
934 ubfm(rd, rn, (reg_size - shift) % reg_size, reg_size - shift - 1);
938 inline void lsr(const Register& rd, const Register& rn, unsigned shift) {
940 ubfm(rd, rn, shift, rd.size() - 1);
945 const Register& rn,
949 VIXL_ASSERT(lsb + width <= rn.size());
950 ubfm(rd, rn, (rd.size() - lsb) & (rd.size() - 1), width - 1);
955 const Register& rn,
959 VIXL_ASSERT(lsb + width <= rn.size());
960 ubfm(rd, rn, lsb, lsb + width - 1);
964 inline void uxtb(const Register& rd, const Register& rn) {
965 ubfm(rd, rn, 0, 7);
969 inline void uxth(const Register& rd, const Register& rn) {
970 ubfm(rd, rn, 0, 15);
974 inline void uxtw(const Register& rd, const Register& rn) {
975 ubfm(rd, rn, 0, 31);
980 const Register& rn,
984 // Conditional select: rd = cond ? rn : rm.
986 const Register& rn,
990 // Conditional select increment: rd = cond ? rn : rm + 1.
992 const Register& rn,
996 // Conditional select inversion: rd = cond ? rn : ~rm.
998 const Register& rn,
1002 // Conditional select negation: rd = cond ? rn : -rm.
1004 const Register& rn,
1014 // Conditional increment: rd = cond ? rn + 1 : rn.
1015 void cinc(const Register& rd, const Register& rn, Condition cond);
1017 // Conditional invert: rd = cond ? ~rn : rn.
1018 void cinv(const Register& rd, const Register& rn, Condition cond);
1020 // Conditional negate: rd = cond ? -rn : rn.
1021 void cneg(const Register& rd, const Register& rn, Condition cond);
1030 void ccmn(const Register& rn,
1036 void ccmp(const Register& rn,
1042 void mul(const Register& rd, const Register& rn, const Register& rm);
1045 void mneg(const Register& rd, const Register& rn, const Register& rm);
1048 void smull(const Register& rd, const Register& rn, const Register& rm);
1055 const Register& rn,
1061 const Register& rn,
1067 const Register& rn,
1073 const Register& rn,
1079 const Register& rn,
1085 const Register& rn,
1090 void sdiv(const Register& rd, const Register& rn, const Register& rm);
1093 void udiv(const Register& rd, const Register& rn, const Register& rm);
1096 void rbit(const Register& rd, const Register& rn);
1099 void rev16(const Register& rd, const Register& rn);
1102 void rev32(const Register& rd, const Register& rn);
1105 void rev(const Register& rd, const Register& rn);
1108 void clz(const Register& rd, const Register& rn);
1111 void cls(const Register& rd, const Register& rn);
1202 void mov(const Register& rd, const Register& rn);
1243 void fmov(const FPRegister& fd, const Register& rn);
1368 void scvtf(const FPRegister& fd, const Register& rn, unsigned fbits = 0);
1371 void ucvtf(const FPRegister& fd, const Register& rn, unsigned fbits = 0);
1407 static Instr Rn(CPURegister rn) {
1408 VIXL_ASSERT(rn.code() != kSPRegInternalCode);
1409 return rn.code() << Rn_offset;
1439 static Instr RnSP(Register rn) {
1440 VIXL_ASSERT(!rn.IsZero());
1441 return (rn.code() & kRegCodeMask) << Rn_offset;
1709 const Register& rn,
1713 const Register& rn,
1724 void ConditionalCompare(const Register& rn,
1732 const Register& rn,
1743 const Register& rn,
1747 const Register& rn,
1752 const Register& rn,
1780 const Register& rn,
1785 const Register& rn,
1799 const Register& rn,
1804 const Register& rn,
1807 const Register& rn,
