Home | History | Annotate | Download | only in a64

Lines Matching refs:reg3

1416                                       const Register& reg3,
1418   RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
1428                                       const FPRegister& reg3,
1430   RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
1447                                       const Register& reg3,
1449   RegList exclude = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
1456                                       const FPRegister& reg3,
1458   RegList excludefp = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
1465                                       const CPURegister& reg3,
1470   const CPURegister regs[] = {reg1, reg2, reg3, reg4};