Lines Matching refs:r12
62 * r12 -- switch index
72 .macro fetch, max_r=MAX_R, labelc=1, labelnc=2, reg=r12 /*{{{*/
73 .ifc \reg,r12 ; .set cc, 1 ; .else ; .set cc, 0 ; .endif
167 * r12 -- temp buffer pointer
176 ldr r12, [pc, r5, LSL #2]
177 add pc, pc, r12
247 ldr r12, [pc, r5, LSL #2]
248 add pc, pc, r12
379 ldr r12, [pc, r5, LSL #2]
380 add pc, pc, r12
577 ldr r12, [pc, r5, LSL #2]
578 add pc, pc, r12
628 ldr r12, [pc, r5, LSL #2]
629 add pc, pc, r12
643 112: add r12, r9, #0x1a0
644 bic r12, r12, #0x200
645 vld1.u16 {d24,d25}, [r12:128]
650 111: add r12, r9, #0x1a8
651 bic r12, r12, #0x200
652 vld1.u16 {d24}, [r12:64]!
653 bic r12, r12, #0x200
654 vld1.u16 {d25}, [r12:64]
659 110: add r12, r9, #0x1b0
660 bic r12, r12, #0x200
661 vld1.u16 {d24,d25}, [r12:128]
666 109: add r12, r9, #0x1b8
667 bic r12, r12, #0x200
668 vld1.u16 {d24}, [r12:64]!
669 bic r12, r12, #0x200
670 vld1.u16 {d25}, [r12:64]
675 108: add r12, r9, #0x1c0
676 bic r12, r12, #0x200
677 vld1.u16 {d24,d25}, [r12:128]
682 107: add r12, r9, #0x1c8
683 bic r12, r12, #0x200
684 vld1.u16 {d24}, [r12:64]!
685 bic r12, r12, #0x200
686 vld1.u16 {d25}, [r12:64]
691 106: add r12, r9, #0x1d0
692 bic r12, r12, #0x200
693 vld1.u16 {d24,d25}, [r12:128]
698 105: add r12, r9, #0x1d8
699 bic r12, r12, #0x200
700 vld1.u16 {d24}, [r12:64]!
701 bic r12, r12, #0x200
702 vld1.u16 {d25}, [r12:64]
707 104: add r12, r9, #0x1e0
708 bic r12, r12, #0x200
709 vld1.u16 {d24,d25}, [r12:128]
714 103: add r12, r9, #0x1e8
715 bic r12, r12, #0x200
716 vld1.u16 {d24}, [r12:64]!
717 bic r12, r12, #0x200
718 vld1.u16 {d25}, [r12:64]
723 102: add r12, r9, #0x1f0
724 bic r12, r12, #0x200
725 vld1.u16 {d24,d25}, [r12:128]
730 101: add r12, r9, #0x1f8
731 bic r12, r12, #0x200
732 vld1.u16 {d24}, [r12:64]
754 add r12, r9, #0x198
755 bic r12, r12, #0x200
756 vld1.u16 {d24}, [r12:64]!
757 bic r12, r12, #0x200
758 vld1.u16 {d25}, [r12:64]
762 ldr r12, [pc, r5, LSL #2]
763 add pc, pc, r12
790 125: add r12, r9, #0x0d0
791 bic r12, r12, #0x200
792 vld1.u16 {d24,d25}, [r12:128]
797 124: add r12, r9, #0x0d8
798 bic r12, r12, #0x200
799 vld1.u16 {d24}, [r12:64]!
800 bic r12, r12, #0x200
801 vld1.u16 {d25}, [r12]
806 123: add r12, r9, #0x0e0
807 bic r12, r12, #0x200
808 vld1.u16 {d24,d25}, [r12:128]
813 122: add r12, r9, #0x0e8
814 bic r12, r12, #0x200
815 vld1.u16 {d24}, [r12:64]!
816 bic r12, r12, #0x200
817 vld1.u16 {d25}, [r12]
822 121: add r12, r9, #0x0f0
823 bic r12, r12, #0x200
824 vld1.u16 {d24,d25}, [r12:128]
829 120: add r12, r9, #0x0f8
830 bic r12, r12, #0x200
831 vld1.u16 {d24}, [r12:64]!
832 bic r12, r12, #0x200
833 vld1.u16 {d25}, [r12]
838 119: add r12, r9, #0x100
839 bic r12, r12, #0x200
840 vld1.u16 {d24,d25}, [r12:128]
845 118: add r12, r9, #0x108
846 bic r12, r12, #0x200
847 vld1.u16 {d24}, [r12:64]!
848 bic r12, r12, #0x200
849 vld1.u16 {d25}, [r12]
854 117: add r12, r9, #0x110
855 bic r12, r12, #0x200
856 vld1.u16 {d24,d25}, [r12:128]
861 116: add r12, r9, #0x118
862 bic r12, r12, #0x200
863 vld1.u16 {d24}, [r12:64]!
864 bic r12, r12, #0x200
865 vld1.u16 {d25}, [r12]
870 115: add r12, r9, #0x120
871 bic r12, r12, #0x200
872 vld1.u16 {d24,d25}, [r12:128]
877 114: add r12, r9, #0x128
878 bic r12, r12, #0x200
879 vld1.u16 {d24}, [r12:64]!
880 bic r12, r12, #0x200
881 vld1.u16 {d25}, [r12]
886 113: add r12, r9, #0x130
887 bic r12, r12, #0x200
888 vld1.u16 {d24,d25}, [r12:128]
893 112: add r12, r9, #0x138
894 bic r12, r12, #0x200
895 vld1.u16 {d24}, [r12:64]!
896 bic r12, r12, #0x200
897 vld1.u16 {d25}, [r12]
898 add r12, r9, #0x1f8
899 bic r12, r12, #0x200
900 vld1.u16 {d26}, [r12:64]
905 111: add r12, r9, #0x140
906 bic r12, r12, #0x200
907 vld1.u16 {d24,d25}, [r12:128]
908 add r12, r9, #0x1f0
909 bic r12, r12, #0x200
910 vld1.u16 {d26,d27}, [r12:128]
915 110: add r12, r9, #0x148
916 bic r12, r12, #0x200
917 vld1.u16 {d24}, [r12:64]!
918 bic r12, r12, #0x200
919 vld1.u16 {d25}, [r12]
920 add r12, r9, #0x1e8
921 bic r12, r12, #0x200
922 vld1.u16 {d26}, [r12:64]!
923 bic r12, r12, #0x200
924 vld1.u16 {d27}, [r12:64]
929 109: add r12, r9, #0x150
930 bic r12, r12, #0x200
931 vld1.u16 {d24,d25}, [r12:128]
932 add r12, r9, #0x1e0
933 bic r12, r12, #0x200
934 vld1.u16 {d26,d27}, [r12:128]
939 108: add r12, r9, #0x158
940 bic r12, r12, #0x200
941 vld1.u16 {d24}, [r12:64]!
942 bic r12, r12, #0x200
943 vld1.u16 {d25}, [r12]
944 add r12, r9, #0x1d8
945 bic r12, r12, #0x200
946 vld1.u16 {d26}, [r12:64]!
947 bic r12, r12, #0x200
948 vld1.u16 {d27}, [r12:64]
953 107: add r12, r9, #0x160
954 bic r12, r12, #0x200
955 vld1.u16 {d24,d25}, [r12:128]
956 add r12, r9, #0x1d0
957 bic r12, r12, #0x200
958 vld1.u16 {d26,d27}, [r12:128]
963 106: add r12, r9, #0x168
964 bic r12, r12, #0x200
965 vld1.u16 {d24}, [r12:64]!
966 bic r12, r12, #0x200
967 vld1.u16 {d25}, [r12]
968 add r12, r9, #0x1c8
969 bic r12, r12, #0x200
970 vld1.u16 {d26}, [r12:64]!
971 bic r12, r12, #0x200
972 vld1.u16 {d27}, [r12:64]
977 105: add r12, r9, #0x170
978 bic r12, r12, #0x200
979 vld1.u16 {d24,d25}, [r12:128]
980 add r12, r9, #0x1c0
981 bic r12, r12, #0x200
982 vld1.u16 {d26,d27}, [r12:128]
987 104: add r12, r9, #0x178
988 bic r12, r12, #0x200
989 vld1.u16 {d24}, [r12:64]!
990 bic r12, r12, #0x200
991 vld1.u16 {d25}, [r12]
992 add r12, r9, #0x1b8
993 bic r12, r12, #0x200
994 vld1.u16 {d26}, [r12:64]!
995 bic r12, r12, #0x200
996 vld1.u16 {d27}, [r12:64]
1001 103: add r12, r9, #0x180
1002 bic r12, r12, #0x200
1003 vld1.u16 {d24,d25}, [r12:128]
1004 add r12, r9, #0x1b0
1005 bic r12, r12, #0x200
1006 vld1.u16 {d26,d27}, [r12:128]
1011 102: add r12, r9, #0x188
1012 bic r12, r12, #0x200
1013 vld1.u16 {d24}, [r12:64]!
1014 bic r12, r12, #0x200
1015 vld1.u16 {d25}, [r12]
1016 add r12, r9, #0x1a8
1017 bic r12, r12, #0x200
1018 vld1.u16 {d26}, [r12:64]!
1019 bic r12, r12, #0x200
1020 vld1.u16 {d27}, [r12:64]
1025 101: add r12, r9, #0x190
1026 bic r12, r12, #0x200
1027 vld1.u16 {d24,d25}, [r12:128]!
1028 bic r12, r12, #0x200
1029 vld1.u16 {d26,d27}, [r12:128]
1069 ands r12, r11, #15
1071 sub r12, r12, #1
1074 add r12, sp, r12, LSL #1
1075 vld1.u16 {d24[]}, [r12]
1076 vld1.u16 {d25[]}, [r12]
1077 vst1.u16 {q12}, [r12]!
1078 vst1.u16 {q12}, [r12]
1087 ands r12, r11, #15
1089 sub r12, r12, #4
1092 add r12, sp, r12, LSL #1
1093 vld1.u64 {d24}, [r12]
1094 vld1.u64 {d25}, [r12]
1095 vst1.u16 {q12}, [r12]!
1096 vst1.u16 {q12}, [r12]
1173 * r12 -- scratch
1194 ands r12, r10, #15
1198 sub r12, sp, r12, LSL #1
1203 vld1.u16 {q10,q11}, [r12]
1363 push {r12,lr}
1371 pop {r12,pc}
1377 sub r12, sp, #0x200
1378 bic r9, r12, #0x3fc
1380 push {r12,lr}
1393 pop {r12,lr}
1394 add sp, r12, #0x200
1412 push {r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
1424 ldr r12, [sp,#124]
1440 vld1.u16 {d0,d1,d2,d3}, [r12]!
1441 vld1.u16 {d4,d5,d6}, [r12]!
1451 pop {r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
1467 push {r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
1479 ldr r12, [sp,#124]
1496 vld1.u16 {d0,d1,d2,d3}, [r12]!
1497 vld1.u16 {d4,d5,d6}, [r12]!
1507 pop {r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
