Lines Matching refs:x4
54 #define TIMPANI_MREF_MREF_PTAT_CURRENT_M 0x4
65 #define TIMPANI_A_CDAC_IDAC_REF_CUR (0x4)
79 #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_10UA_NORMAL_OP 0x4
91 #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_5UA 0x4
160 #define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_M 0x4
204 #define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_M 0x4
264 #define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_M 0x4
307 #define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_M 0x4
354 #define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_M 0x4
381 #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_025V 0x4
429 #define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_M 0x4
472 #define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_M 0x4
614 #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_32 0x4
625 #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_M 0x4
721 #define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_M 0x4
750 #define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_M 0x4
787 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_15_6NS 0x4
826 #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_120UA 0x4
865 #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_925V 0x4
877 #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_2V 0x4
909 #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR4 0x4
1000 #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_5UA 0x4
1012 #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_5UA_NORMAL_OP 0x4
1051 #define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_M 0x4
1092 #define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_M 0x4
1120 #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_7_5UA 0x4
1132 #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_7_5UA 0x4
1195 #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_25UA 0x4
1217 #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_25UA 0x4
1246 #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4
1259 #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4
1276 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_POR 0x4
1306 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_M 0x4
1352 #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_M 0x4
1399 #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_M 0x4
1426 #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_4_5 0x4
1492 #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_4_5 0x4
1559 #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_4_5 0x4
1630 #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_4_5 0x4
1701 #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_18DB 0x4
1724 #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_18DB 0x4
1769 #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_M 0x4
1815 #define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_M 0x4
1859 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_M 0x4
1902 #define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_M 0x4
1949 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_M 0x4
2012 #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_341_V 0x4
2156 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_M 0x4
2192 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_M 0x4
2236 x4
2265 #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1279 0x4
2287 #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1279 0x4
2332 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_M 0x4
2369 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_M 0x4
2412 #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_4 0x4
2441 #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1279 0x4
2464 #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1279 0x4
2491 #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_100PER 0x4
2507 #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_150MA 0x4
2645 #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_2 0x4
2657 #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_2 0x4
2724 #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_M 0x4
2752 x4
2815 #define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VICM_TO_ATEST1 0x4
2826 #define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VOCM_TO_ATEST2 0x4
2851 #define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VICM_TO_ATEST1 0x4
2862 #define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VOCM_TO_ATEST2 0x4
2959 #define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_1 0x4
2976 #define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_1 0x4
3015 #define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_M 0x4
3042 #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_BREAK_BEFORE_MAKE_OUT_CP 0x4
3065 #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_BREAK_BEFORE_MAKE_OUT_CN 0x4
3112 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_M 0x4
3144 #define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_M 0x4
3225 #define TIMPANI_CDC_CH_CTL_TX1_EN_L_M 0x4
3304 #define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_M 0x4
3339 #define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_M 0x4
3372 #define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_M 0x4
3402 #define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_M 0x4
3417 #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_6 0x4
3447 #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_6 0x4
3456 #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_6 0x4
3479 #define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_M 0x4
3501 #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_6 0x4
3510 #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_6 0x4
3532 #define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_M 0x4
3549 #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_6 0x4
3570 #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_6 0x4
3701 #define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_M 0x4
3717 #define TIMPANI_CDC_ST_MIXING_TX2_L_M 0x4
3769 #define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_DMIC 0x4
3776 #define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_M 0x4
3887 #define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_M 0x4
3909 #define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_M 0x4
3930 #define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_M 0x4
3946 #define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_M 0x4
4002 #define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_M 0x4
4024 #define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_M 0x4
4090 #define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_M 0x4
4131 #define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_M 0x4
4264 #define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_M 0x4
4305 #define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_M 0x4
4490 #define TIMPANI_CDC_COMP_CTL1_LO_L_EN_M 0x4
4584 #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_M 0x4
