Lines Matching full:significant
3881 significant 8 bits of a 24 bit word are placed into the least
3882 significant 8 bits of the opcode. */
3886 significant 7 bits of a 16 bit word are placed into the least
3887 significant 7 bits of the opcode. */
3891 significant 9 bits of a 16 bit word are placed into the least
3892 significant 9 bits of the opcode. */
3899 significant 16 bits of a 23-bit extended address are placed into
3904 significant 7 bits of a 23-bit extended address are placed into
5152 /* AArch64 MOV[NZK] instruction with most significant bits 0 to 15
5156 /* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
5161 /* AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
5165 /* AArch64 MOV[NZK] instruction with most significant bits 16 to 31
5169 /* AArch64 MOV[NZK] instruction with less significant bits 16 to 31
5173 /* AArch64 MOV[NZ] instruction with most significant bits 16 to 31
5178 /* AArch64 MOV[NZK] instruction with most significant bits 32 to 47
5182 /* AArch64 MOV[NZK] instruction with less significant bits 32 to 47
5186 /* AArch64 MOV[NZ] instruction with most significant bits 32 to 47
5476 /* Adapteva EPIPHANY - 16 most-significant
5479 /* Adapteva EPIPHANY - 16 least-significant bits of absolute address */
