Lines Matching full:cmeq
3052 T ? C T ? C T ? C
T ? C ? @ /tmp/AOSP-toolchain/build/../binutils/binutils-2.24/opcodes/aarch64-opc.c qseq_list[0][known_idx] == AARCH64_OPND_NIL operand_variant_qualifier_p (qualifier) == 1 opcode->operands[idx] == opnd->type && opnd->type == type idx == 1 && (aarch64_get_operand_class (opnds[0].type) == AARCH64_OPND_CLASS_SYSTEM) stack pointer register expected negative or unaligned offset expected /tmp/AOSP-toolchain/build/../binutils/binutils-2.24/opcodes/aarch64-opc.h ls[size - 1] != (unsigned char)-1 shift amount expected to be 0 or 12 idx == 1 && opnds[0].type == AARCH64_OPND_Rd shift amount should be a multiple of 16 negative immediate value not allowed idx == 3 && opnds[idx-1].type == AARCH64_OPND_IMM && opnds[0].type == AARCH64_OPND_Rd qualifier_value_in_range_constraint_p (qualifier) == 1 shift amount expected to be 0 or 16 floating-point immediate expected idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4 opnd->shifter.operator_present || opnd->shifter.kind == AARCH64_MOD_LSL opnd->qualifier == AARCH64_OPND_QLF_W || opnd->qualifier == AARCH64_OPND_QLF_X opnd->qualifier == AARCH64_OPND_QLF_W || opnd->qualifier == AARCH64_OPND_QLF_WSP || opnd->qualifier == AARCH64_OPND_QLF_X || opnd->qualifier == AARCH64_OPND_QLF_SP opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index num_regs >= 1 && num_regs <= 4 {v%d.%s, v%d.%s, v%d.%s, v%d.%s}%s 0 ,%s #%d [%s,%c%d%s] ,%s value < 16 i >= 0 && i <= 6 nb_imms == 5334 extraneous register missing register unexpected address writeback address writeback expected opnd->addr.writeback == 0 immediate offset idx == 1 invalid register offset invalid post-increment amount invalid shift amount invalid extend/shift operator width > 0 && width < 32 immediate out of range num >= 1 && num <= 4 immediate value invalid shift operator shift amount immediate zero expected idx == 2 shift is not permitted invalid value for immediate register number register element index idx == 1 || idx == 2 extend operator expected missing extend operator 'LSL' operator not allowed W register expected shift operator expected 'ROR' operator not allowed spsr_el1 spsel %s %s, %s #%d %s, %s %s%d v%d.%s v%d.%s[%d] v%d.d[1] [%d] {v%d.%s-v%d.%s}%s {v%d.%s}%s {v%d.%s, v%d.%s}%s {v%d.%s, v%d.%s, v%d.%s}%s C%d #%li #0x%-20x // #%d #0x%-20lx // #%li #0.0 #0x%lx, lsl #%d #0x%lx #0x%lx, %s #%d #%.18e #0x%x [%s], x%d [%s], #%d [%s] [%s,#%d]! [%s],#%d [%s,#%d] s%u_%u_c%u_c%u_%u #0x%02x aarch64_pstatefields[i].name adc adcs sbc ngc sbcs ngcs add adds cmn sub subs cmp mov neg negs saddlv smaxv sminv addv uaddlv umaxv uminv fmaxnmv fmaxv fminnmv fminv saddl saddl2 saddw saddw2 ssubl ssubl2 ssubw ssubw2 addhn addhn2 sabal sabal2 subhn subhn2 sabdl sabdl2 smlal smlal2 sqdmlal sqdmlal2 smlsl smlsl2 sqdmlsl sqdmlsl2 smull smull2 sqdmull sqdmull2 pmull pmull2 uaddl uaddl2 uaddw uaddw2 usubl usubl2 usubw usubw2 raddhn raddhn2 uabal uabal2 rsubhn rsubhn2 uabdl uabdl2 umlal umlal2 umlsl umlsl2 umull umull2 mul sqdmulh sqrdmulh fmla fmls fmul mla mls fmulx ext movi orr fmov mvni bic dup smov umov ins rev64 rev16 saddlp suqadd cls cnt sadalp sqabs cmgt cmeq