Lines Matching refs:Rd
355 void ArmToMipsAssembler::protectConditionalOperands(int Rd)
357 if (Rd == cond.r1) {
361 if (cond.type == CMP_COND && Rd == cond.r2) {
418 int s, int Rd, int Rn, uint32_t Op2)
424 protectConditionalOperands(Rd);
435 mMips->AND(Rd, Rn, src);
437 mMips->ANDI(Rd, Rn, src);
444 mMips->ADDU(Rd, Rn, src);
446 mMips->ADDIU(Rd, Rn, src);
453 mMips->SUBU(Rd, Rn, src);
455 mMips->SUBIU(Rd, Rn, src);
461 mMips->XOR(Rd, Rn, src);
463 mMips->XORI(Rd, Rn, src);
469 mMips->OR(Rd, Rn, src);
471 mMips->ORI(Rd, Rn, src);
482 mMips->AND(Rd, Rn, R_at);
491 mMips->SUBU(Rd, src, Rn); // subu with the parameters reversed
496 mMips->MOVE(Rd, Op2);
499 mMips->LUI(Rd, (amode.value >> 16));
501 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
504 mMips->ORI(Rd, 0, amode.value);
508 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
509 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
510 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
512 mMips->ROTR(Rd, amode.reg, amode.value);
514 mMips->RORIsyn(Rd, amode.reg, amode.value);
527 mMips->NOR(Rd, Op2, 0); // NOT is NOR with 0
531 mMips->LUI(Rd, (amode.value >> 16));
533 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
536 mMips->ORI(Rd, 0, amode.value);
540 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
541 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
542 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
544 Rd, amode.reg, amode.value);
546 mMips->RORIsyn(Rd, amode.reg, amode.value);
555 mMips->NOR(Rd, Rd, 0); // NOT is NOR with 0
601 cond.r1 = Rd;
614 int Rd, int Rm, int Rs, int Rn) {
619 mMips->ADDU(Rd, R_at, Rn);
622 cond.r1 = Rd;
627 int Rd, int Rm, int Rs) {
629 mMips->MUL(Rd, Rm, Rs);
632 cond.r1 = Rd;
768 void ArmToMipsAssembler::LDR(int cc, int Rd, int Rn, uint32_t offset)
782 mMips->LW(Rd, Rn, amode.value);
791 mMips->LW(Rd, Rn, 0);
797 mMips->LW(Rd, R_at, 0);
802 void ArmToMipsAssembler::LDRB(int cc, int Rd, int Rn, uint32_t offset)
813 mMips->LBU(Rd, Rn, amode.value);
819 mMips->LBU(Rd, Rn, 0);
825 mMips->LBU(Rd, R_at, 0);
831 void ArmToMipsAssembler::STR(int cc, int Rd, int Rn, uint32_t offset)
849 mMips->SW(Rd, Rn, 0);
852 mMips->SW(Rd, Rn, amode.value);
856 mMips->SW(Rd, Rn, 0);
862 mMips->SW(Rd, R_at, 0);
867 void ArmToMipsAssembler::STRB(int cc, int Rd, int Rn, uint32_t offset)
878 mMips->SB(Rd, Rn, amode.value);
884 mMips->SB(Rd, Rn, 0);
890 mMips->SB(Rd, R_at, 0);
895 void ArmToMipsAssembler::LDRH(int cc, int Rd, int Rn, uint32_t offset)
905 mMips->LHU(Rd, Rn, amode.value);
908 mMips->LHU(Rd, Rn, 0);
918 mMips->LHU(Rd, R_at, 0);
923 void ArmToMipsAssembler::LDRSB(int cc, int Rd, int Rn, uint32_t offset)
930 void ArmToMipsAssembler::LDRSH(int cc, int Rd, int Rn, uint32_t offset)
937 void ArmToMipsAssembler::STRH(int cc, int Rd, int Rn, uint32_t offset)
947 mMips->SH(Rd, Rn, amode.value);
950 mMips->SH(Rd, Rn, 0);
960 mMips->SH(Rd, R_at, 0);
1005 void ArmToMipsAssembler::SWP(int cc, int Rn, int Rd, int Rm) {
1006 // *mPC++ = (cc<<28) | (2<<23) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
1012 void ArmToMipsAssembler::SWPB(int cc, int Rn, int Rd, int Rm) {
1013 // *mPC++ = (cc<<28) | (2<<23) | (1<<22) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
1042 void ArmToMipsAssembler::CLZ(int cc, int Rd, int Rm)
1045 mMips->CLZ(Rd, Rm);
1048 void ArmToMipsAssembler::QADD(int cc, int Rd, int Rm, int Rn)
1050 // *mPC++ = (cc<<28) | 0x1000050 | (Rn<<16) | (Rd<<12) | Rm;
1056 void ArmToMipsAssembler::QDADD(int cc, int Rd, int Rm, int Rn)
1058 // *mPC++ = (cc<<28) | 0x1400050 | (Rn<<16) | (Rd<<12) | Rm;
1064 void ArmToMipsAssembler::QSUB(int cc, int Rd, int Rm, int Rn)
1066 // *mPC++ = (cc<<28) | 0x1200050 | (Rn<<16) | (Rd<<12) | Rm;
1072 void ArmToMipsAssembler::QDSUB(int cc, int Rd, int Rm, int Rn)
1074 // *mPC++ = (cc<<28) | 0x1600050 | (Rn<<16) | (Rd<<12) | Rm;
1082 int Rd, int Rm, int Rs)
1116 mMips->MUL(Rd, R_at, R_at2);
1121 int Rd, int Rm, int Rs)
1136 mMips->MFHI(Rd);
1139 // 16 x 16 signed multiply, accumulate: Rd = Rm{16} * Rs{16} + Rn
1141 int Rd, int Rm, int Rs, int Rn)
1177 mMips->ADDU(Rd, R_at, Rn);
1190 int Rd, int Rm, int Rs, int Rn)
1192 // *mPC++ = (cc<<28) | 0x1200080 | (Rd<<16) | (Rn<<12) | (Rs<<8) | (y<<4) | Rm;
1199 void ArmToMipsAssembler::UXTB16(int cc, int Rd, int Rm, int rotate)
1203 //Rd[31:16] := ZeroExtend((Rm ROR (8 * sh))[23:16]),
1204 //Rd[15:0] := ZeroExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.
1207 mMips->AND(Rd, Rm, 0x00FF00FF);
1210 void ArmToMipsAssembler::UBFX(int cc, int Rd, int Rn, int lsb, int width)
1439 void MIPSAssembler::ADDU(int Rd, int Rs, int Rt)
1442 | (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF);
1445 // MD00086 pdf says this is: ADDIU rt, rs, imm -- they do not use Rd
1452 void MIPSAssembler::SUBU(int Rd, int Rs, int Rt)
1455 (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF) ;
1465 void MIPSAssembler::NEGU(int Rd, int Rs) // really subu(d, zero, s)
1467 MIPSAssembler::SUBU(Rd, 0, Rs);
1470 void MIPSAssembler::MUL(int Rd, int Rs, int Rt)
1473 (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF) ;
1508 void MIPSAssembler::SEB(int Rd, int Rt) // sign-extend byte (mips32r2)
1511 (Rt<<RT_SHF) | (Rd<<RD_SHF);
1514 void MIPSAssembler::SEH(int Rd, int Rt) // sign-extend half-word (mips32r2)
1517 (Rt<<RT_SHF) | (Rd<<RD_SHF);
1527 void MIPSAssembler::SLT(int Rd, int Rs, int Rt)
1530 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1539 void MIPSAssembler::SLTU(int Rd, int Rs, int Rt)
1542 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1557 void MIPSAssembler::AND(int Rd, int Rs, int Rt)
1560 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1569 void MIPSAssembler::OR(int Rd, int Rs, int Rt)
1572 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1580 void MIPSAssembler::NOR(int Rd, int Rs, int Rt)
1583 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1586 void MIPSAssembler::NOT(int Rd, int Rs)
1588 MIPSAssembler::NOR(Rd, Rs, 0); // NOT(d,s) = NOR(d,s,zero)
1591 void MIPSAssembler::XOR(int Rd, int Rs, int Rt)
1594 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1602 void MIPSAssembler::SLL(int Rd, int Rt, int shft)
1605 (Rd<<RD_SHF) | (Rt<<RT_SHF) | (shft<<RE_SHF);
1608 void MIPSAssembler::SLLV(int Rd, int Rt, int Rs)
1611 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1614 void MIPSAssembler::SRL(int Rd, int Rt, int shft)
1617 (Rd<<RD_SHF) | (Rt<<RT_SHF) | (shft<<RE_SHF);
1620 void MIPSAssembler::SRLV(int Rd, int Rt, int Rs)
1623 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1626 void MIPSAssembler::SRA(int Rd, int Rt, int shft)
1629 (Rd<<RD_SHF) | (Rt<<RT_SHF) | (shft<<RE_SHF);
1632 void MIPSAssembler::SRAV(int Rd, int Rt, int Rs)
1635 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1638 void MIPSAssembler::ROTR(int Rd, int Rt, int shft) // mips32r2
1642 (1<<RS_SHF) | (Rd<<RD_SHF) | (Rt<<RT_SHF) | (shft<<RE_SHF);
1645 void MIPSAssembler::ROTRV(int Rd, int Rt, int Rs) // mips32r2
1649 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF) | (1<<RE_SHF);
1653 void MIPSAssembler::RORsyn(int Rd, int Rt, int Rs)
1658 MIPSAssembler::SRLV(Rd, Rt, Rs);
1659 MIPSAssembler::OR(Rd, Rd, R_at2);
1663 void MIPSAssembler::RORIsyn(int Rd, int Rt, int rot)
1668 MIPSAssembler::SRL(Rd, Rt, rot);
1669 MIPSAssembler::OR(Rd, Rd, R_at2);
1672 void MIPSAssembler::CLO(int Rd, int Rs)
1674 // Rt field must have same gpr # as Rd
1676 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rd<<RT_SHF);
1679 void MIPSAssembler::CLZ(int Rd, int Rs)
1681 // Rt field must have same gpr # as Rd
1683 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rd<<RT_SHF);
1686 void MIPSAssembler::WSBH(int Rd, int Rt) // mips32r2
1689 (Rt<<RT_SHF) | (Rd<<RD_SHF);
1753 void MIPSAssembler::MOVE(int Rd, int Rs)
1755 // encoded as "or rd, rs, zero"
1757 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (0<<RT_SHF);
1760 void MIPSAssembler::MOVN(int Rd, int Rs, int Rt)
1763 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1766 void MIPSAssembler::MOVZ(int Rd, int Rs, int Rt)
1769 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF);
1772 void MIPSAssembler::MFHI(int Rd)
1774 *mPC++ = (spec_op<<OP_SHF) | (mfhi_fn<<FUNC_SHF) | (Rd<<RD_SHF);
1777 void MIPSAssembler::MFLO(int Rd)
1779 *mPC++ = (spec_op<<OP_SHF) | (mflo_fn<<FUNC_SHF) | (Rd<<RD_SHF);
