Lines Matching refs:Rd
414 void dataOpTest(dataOpTest_t test, ARMAssemblerInterface *a64asm, uint32_t Rd = 0,
428 regs[Rd] = test.RdValue;
450 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break;
451 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break;
452 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break;
453 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break;
454 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break;
455 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break;
456 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break;
457 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
459 case INSTR_MOV: a64asm->MOV(test.cond, test.setFlags,Rd,op2); break;
460 case INSTR_MVN: a64asm->MVN(test.cond, test.setFlags,Rd,op2); break;
461 case INSTR_SMULBB:a64asm->SMULBB(test.cond, Rd,Rm,Rs); break;
462 case INSTR_SMULBT:a64asm->SMULBT(test.cond, Rd,Rm,Rs); break;
463 case INSTR_SMULTB:a64asm->SMULTB(test.cond, Rd,Rm,Rs); break;
464 case INSTR_SMULTT:a64asm->SMULTT(test.cond, Rd,Rm,Rs); break;
465 case INSTR_SMULWB:a64asm->SMULWB(test.cond, Rd,Rm,Rs); break;
466 case INSTR_SMULWT:a64asm->SMULWT(test.cond, Rd,Rm,Rs); break;
467 case INSTR_SMLABB:a64asm->SMLABB(test.cond, Rd,Rm,Rs,Rn); break;
468 case INSTR_UXTB16:a64asm->UXTB16(test.cond, Rd,Rm,test.shiftAmount); break;
473 a64asm->UBFX(test.cond, Rd,Rn,lsb, width);
476 case INSTR_ADDR_ADD: a64asm->ADDR_ADD(test.cond, test.setFlags, Rd,Rn,op2); break;
477 case INSTR_ADDR_SUB: a64asm->ADDR_SUB(test.cond, test.setFlags, Rd,Rn,op2); break;
490 /* Check if all regs except Rd is same */
493 if(i == Rd) continue;
502 if(test.checkRd == 1 && (uint64_t)regs[Rd] != test.postRdValue)
505 test.id, test.postRdValue, regs[Rd]);
520 uint32_t Rd = 0, uint32_t Rn = 1,uint32_t Rm = 2)
533 regs[Rd] = test.RdValue;
585 case INSTR_LDR: a64asm->LDR(test.cond, Rd,Rn,op2); break;
586 case INSTR_LDRB: a64asm->LDRB(test.cond, Rd,Rn,op2); break;
587 case INSTR_LDRH: a64asm->LDRH(test.cond, Rd,Rn,op2); break;
588 case INSTR_ADDR_LDR: a64asm->ADDR_LDR(test.cond, Rd,Rn,op2); break;
589 case INSTR_STR: a64asm->STR(test.cond, Rd,Rn,op2); break;
590 case INSTR_STRB: a64asm->STRB(test.cond, Rd,Rn,op2); break;
591 case INSTR_STRH: a64asm->STRH(test.cond, Rd,Rn,op2); break;
592 case INSTR_ADDR_STR: a64asm->ADDR_STR(test.cond, Rd,Rn,op2); break;
606 /* Check if all regs except Rd/Rn are same */
609 if(i == Rd || i == Rn) continue;
619 if((uint64_t)regs[Rd] != test.postRdValue)
622 "Expected in Rd(0x%"PRIx64"), Actual(0x%"PRIx64")\n",
623 test.id, test.postRdValue, regs[Rd]);
752 uint32_t Rd, Rm, Rs, Rn;
759 for(Rd = 0; Rd < numRegs; ++Rd)
767 if(Rd == Rn || Rd == Rm || Rd == Rs) continue;
770 printf("Testing combination Rd(%d), Rn(%d),"
772 reg_list[Rd], reg_list[Rn], reg_list[Rm], reg_list[Rs]);
773 dataOpTest(dataOpTests[i], &a64asm, reg_list[Rd],
