1 /* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #include "codegen_arm64.h" 18 19 #include <inttypes.h> 20 21 #include <string> 22 23 #include "dex/compiler_internals.h" 24 #include "dex/quick/mir_to_lir-inl.h" 25 #include "dex/reg_storage_eq.h" 26 27 namespace art { 28 29 static constexpr RegStorage core_regs_arr[] = 30 {rs_w0, rs_w1, rs_w2, rs_w3, rs_w4, rs_w5, rs_w6, rs_w7, 31 rs_w8, rs_w9, rs_w10, rs_w11, rs_w12, rs_w13, rs_w14, rs_w15, 32 rs_w16, rs_w17, rs_w18, rs_w19, rs_w20, rs_w21, rs_w22, rs_w23, 33 rs_w24, rs_w25, rs_w26, rs_w27, rs_w28, rs_w29, rs_w30, rs_w31, 34 rs_wzr}; 35 static constexpr RegStorage core64_regs_arr[] = 36 {rs_x0, rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7, 37 rs_x8, rs_x9, rs_x10, rs_x11, rs_x12, rs_x13, rs_x14, rs_x15, 38 rs_x16, rs_x17, rs_x18, rs_x19, rs_x20, rs_x21, rs_x22, rs_x23, 39 rs_x24, rs_x25, rs_x26, rs_x27, rs_x28, rs_x29, rs_x30, rs_x31, 40 rs_xzr}; 41 static constexpr RegStorage sp_regs_arr[] = 42 {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7, 43 rs_f8, rs_f9, rs_f10, rs_f11, rs_f12, rs_f13, rs_f14, rs_f15, 44 rs_f16, rs_f17, rs_f18, rs_f19, rs_f20, rs_f21, rs_f22, rs_f23, 45 rs_f24, rs_f25, rs_f26, rs_f27, rs_f28, rs_f29, rs_f30, rs_f31}; 46 static constexpr RegStorage dp_regs_arr[] = 47 {rs_d0, rs_d1, rs_d2, rs_d3, rs_d4, rs_d5, rs_d6, rs_d7, 48 rs_d8, rs_d9, rs_d10, rs_d11, rs_d12, rs_d13, rs_d14, rs_d15, 49 rs_d16, rs_d17, rs_d18, rs_d19, rs_d20, rs_d21, rs_d22, rs_d23, 50 rs_d24, rs_d25, rs_d26, rs_d27, rs_d28, rs_d29, rs_d30, rs_d31}; 51 // Note: we are not able to call to C function since rs_xSELF is a special register need to be 52 // preserved but would be scratched by native functions follow aapcs64. 53 static constexpr RegStorage reserved_regs_arr[] = 54 {rs_wSUSPEND, rs_wSELF, rs_wsp, rs_wLR, rs_wzr}; 55 static constexpr RegStorage reserved64_regs_arr[] = 56 {rs_xSUSPEND, rs_xSELF, rs_sp, rs_xLR, rs_xzr}; 57 static constexpr RegStorage core_temps_arr[] = 58 {rs_w0, rs_w1, rs_w2, rs_w3, rs_w4, rs_w5, rs_w6, rs_w7, 59 rs_w8, rs_w9, rs_w10, rs_w11, rs_w12, rs_w13, rs_w14, rs_w15, rs_w16, 60 rs_w17}; 61 static constexpr RegStorage core64_temps_arr[] = 62 {rs_x0, rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7, 63 rs_x8, rs_x9, rs_x10, rs_x11, rs_x12, rs_x13, rs_x14, rs_x15, rs_x16, 64 rs_x17}; 65 static constexpr RegStorage sp_temps_arr[] = 66 {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7, 67 rs_f16, rs_f17, rs_f18, rs_f19, rs_f20, rs_f21, rs_f22, rs_f23, 68 rs_f24, rs_f25, rs_f26, rs_f27, rs_f28, rs_f29, rs_f30, rs_f31}; 69 static constexpr RegStorage dp_temps_arr[] = 70 {rs_d0, rs_d1, rs_d2, rs_d3, rs_d4, rs_d5, rs_d6, rs_d7, 71 rs_d16, rs_d17, rs_d18, rs_d19, rs_d20, rs_d21, rs_d22, rs_d23, 72 rs_d24, rs_d25, rs_d26, rs_d27, rs_d28, rs_d29, rs_d30, rs_d31}; 73 74 static constexpr ArrayRef<const RegStorage> core_regs(core_regs_arr); 75 static constexpr ArrayRef<const RegStorage> core64_regs(core64_regs_arr); 76 static constexpr ArrayRef<const RegStorage> sp_regs(sp_regs_arr); 77 static constexpr ArrayRef<const RegStorage> dp_regs(dp_regs_arr); 78 static constexpr ArrayRef<const RegStorage> reserved_regs(reserved_regs_arr); 79 static constexpr ArrayRef<const RegStorage> reserved64_regs(reserved64_regs_arr); 80 static constexpr ArrayRef<const RegStorage> core_temps(core_temps_arr); 81 static constexpr ArrayRef<const RegStorage> core64_temps(core64_temps_arr); 82 static constexpr ArrayRef<const RegStorage> sp_temps(sp_temps_arr); 83 static constexpr ArrayRef<const RegStorage> dp_temps(dp_temps_arr); 84 85 RegLocation Arm64Mir2Lir::LocCReturn() { 86 return arm_loc_c_return; 87 } 88 89 RegLocation Arm64Mir2Lir::LocCReturnRef() { 90 return arm_loc_c_return_ref; 91 } 92 93 RegLocation Arm64Mir2Lir::LocCReturnWide() { 94 return arm_loc_c_return_wide; 95 } 96 97 RegLocation Arm64Mir2Lir::LocCReturnFloat() { 98 return arm_loc_c_return_float; 99 } 100 101 RegLocation Arm64Mir2Lir::LocCReturnDouble() { 102 return arm_loc_c_return_double; 103 } 104 105 // Return a target-dependent special register. 106 RegStorage Arm64Mir2Lir::TargetReg(SpecialTargetRegister reg) { 107 RegStorage res_reg = RegStorage::InvalidReg(); 108 switch (reg) { 109 case kSelf: res_reg = rs_wSELF; break; 110 case kSuspend: res_reg = rs_wSUSPEND; break; 111 case kLr: res_reg = rs_wLR; break; 112 case kPc: res_reg = RegStorage::InvalidReg(); break; 113 case kSp: res_reg = rs_wsp; break; 114 case kArg0: res_reg = rs_w0; break; 115 case kArg1: res_reg = rs_w1; break; 116 case kArg2: res_reg = rs_w2; break; 117 case kArg3: res_reg = rs_w3; break; 118 case kArg4: res_reg = rs_w4; break; 119 case kArg5: res_reg = rs_w5; break; 120 case kArg6: res_reg = rs_w6; break; 121 case kArg7: res_reg = rs_w7; break; 122 case kFArg0: res_reg = rs_f0; break; 123 case kFArg1: res_reg = rs_f1; break; 124 case kFArg2: res_reg = rs_f2; break; 125 case kFArg3: res_reg = rs_f3; break; 126 case kFArg4: res_reg = rs_f4; break; 127 case kFArg5: res_reg = rs_f5; break; 128 case kFArg6: res_reg = rs_f6; break; 129 case kFArg7: res_reg = rs_f7; break; 130 case kRet0: res_reg = rs_w0; break; 131 case kRet1: res_reg = rs_w1; break; 132 case kInvokeTgt: res_reg = rs_wLR; break; 133 case kHiddenArg: res_reg = rs_wIP1; break; 134 case kHiddenFpArg: res_reg = RegStorage::InvalidReg(); break; 135 case kCount: res_reg = RegStorage::InvalidReg(); break; 136 default: res_reg = RegStorage::InvalidReg(); 137 } 138 return res_reg; 139 } 140 141 /* 142 * Decode the register id. This routine makes assumptions on the encoding made by RegStorage. 143 */ 144 ResourceMask Arm64Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const { 145 // TODO(Arm64): this function depends too much on the internal RegStorage encoding. Refactor. 146 147 // Check if the shape mask is zero (i.e. invalid). 148 if (UNLIKELY(reg == rs_wzr || reg == rs_xzr)) { 149 // The zero register is not a true register. It is just an immediate zero. 150 return kEncodeNone; 151 } 152 153 return ResourceMask::Bit( 154 // FP register starts at bit position 32. 155 (reg.IsFloat() ? kArm64FPReg0 : 0) + reg.GetRegNum()); 156 } 157 158 ResourceMask Arm64Mir2Lir::GetPCUseDefEncoding() const { 159 // Note: On arm64, we are not able to set pc except branch instructions, which is regarded as a 160 // kind of barrier. All other instructions only use pc, which has no dependency between any 161 // of them. So it is fine to just return kEncodeNone here. 162 return kEncodeNone; 163 } 164 165 // Arm64 specific setup. TODO: inline?: 166 void Arm64Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, 167 ResourceMask* use_mask, ResourceMask* def_mask) { 168 DCHECK_EQ(cu_->instruction_set, kArm64); 169 DCHECK(!lir->flags.use_def_invalid); 170 171 // Note: REG_USE_PC is ignored, the reason is the same with what we do in GetPCUseDefEncoding(). 172 // These flags are somewhat uncommon - bypass if we can. 173 if ((flags & (REG_DEF_SP | REG_USE_SP | REG_DEF_LR)) != 0) { 174 if (flags & REG_DEF_SP) { 175 def_mask->SetBit(kArm64RegSP); 176 } 177 178 if (flags & REG_USE_SP) { 179 use_mask->SetBit(kArm64RegSP); 180 } 181 182 if (flags & REG_DEF_LR) { 183 def_mask->SetBit(kArm64RegLR); 184 } 185 } 186 } 187 188 ArmConditionCode Arm64Mir2Lir::ArmConditionEncoding(ConditionCode ccode) { 189 ArmConditionCode res; 190 switch (ccode) { 191 case kCondEq: res = kArmCondEq; break; 192 case kCondNe: res = kArmCondNe; break; 193 case kCondCs: res = kArmCondCs; break; 194 case kCondCc: res = kArmCondCc; break; 195 case kCondUlt: res = kArmCondCc; break; 196 case kCondUge: res = kArmCondCs; break; 197 case kCondMi: res = kArmCondMi; break; 198 case kCondPl: res = kArmCondPl; break; 199 case kCondVs: res = kArmCondVs; break; 200 case kCondVc: res = kArmCondVc; break; 201 case kCondHi: res = kArmCondHi; break; 202 case kCondLs: res = kArmCondLs; break; 203 case kCondGe: res = kArmCondGe; break; 204 case kCondLt: res = kArmCondLt; break; 205 case kCondGt: res = kArmCondGt; break; 206 case kCondLe: res = kArmCondLe; break; 207 case kCondAl: res = kArmCondAl; break; 208 case kCondNv: res = kArmCondNv; break; 209 default: 210 LOG(FATAL) << "Bad condition code " << ccode; 211 res = static_cast<ArmConditionCode>(0); // Quiet gcc 212 } 213 return res; 214 } 215 216 static const char *shift_names[4] = { 217 "lsl", 218 "lsr", 219 "asr", 220 "ror" 221 }; 222 223 static const char* extend_names[8] = { 224 "uxtb", 225 "uxth", 226 "uxtw", 227 "uxtx", 228 "sxtb", 229 "sxth", 230 "sxtw", 231 "sxtx", 232 }; 233 234 /* Decode and print a register extension (e.g. ", uxtb #1") */ 235 static void DecodeRegExtendOrShift(int operand, char *buf, size_t buf_size) { 236 if ((operand & (1 << 6)) == 0) { 237 const char *shift_name = shift_names[(operand >> 7) & 0x3]; 238 int amount = operand & 0x3f; 239 snprintf(buf, buf_size, ", %s #%d", shift_name, amount); 240 } else { 241 const char *extend_name = extend_names[(operand >> 3) & 0x7]; 242 int amount = operand & 0x7; 243 if (amount == 0) { 244 snprintf(buf, buf_size, ", %s", extend_name); 245 } else { 246 snprintf(buf, buf_size, ", %s #%d", extend_name, amount); 247 } 248 } 249 } 250 251 #define BIT_MASK(w) ((UINT64_C(1) << (w)) - UINT64_C(1)) 252 253 static uint64_t RotateRight(uint64_t value, unsigned rotate, unsigned width) { 254 DCHECK_LE(width, 64U); 255 rotate &= 63; 256 value = value & BIT_MASK(width); 257 return ((value & BIT_MASK(rotate)) << (width - rotate)) | (value >> rotate); 258 } 259 260 static uint64_t RepeatBitsAcrossReg(bool is_wide, uint64_t value, unsigned width) { 261 unsigned i; 262 unsigned reg_size = (is_wide) ? 64 : 32; 263 uint64_t result = value & BIT_MASK(width); 264 for (i = width; i < reg_size; i *= 2) { 265 result |= (result << i); 266 } 267 DCHECK_EQ(i, reg_size); 268 return result; 269 } 270 271 /** 272 * @brief Decode an immediate in the form required by logical instructions. 273 * 274 * @param is_wide Whether @p value encodes a 64-bit (as opposed to 32-bit) immediate. 275 * @param value The encoded logical immediates that is to be decoded. 276 * @return The decoded logical immediate. 277 * @note This is the inverse of Arm64Mir2Lir::EncodeLogicalImmediate(). 278 */ 279 uint64_t Arm64Mir2Lir::DecodeLogicalImmediate(bool is_wide, int value) { 280 unsigned n = (value >> 12) & 0x01; 281 unsigned imm_r = (value >> 6) & 0x3f; 282 unsigned imm_s = (value >> 0) & 0x3f; 283 284 // An integer is constructed from the n, imm_s and imm_r bits according to 285 // the following table: 286 // 287 // N imms immr size S R 288 // 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr) 289 // 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr) 290 // 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr) 291 // 0 110sss xxxrrr 8 UInt(sss) UInt(rrr) 292 // 0 1110ss xxxxrr 4 UInt(ss) UInt(rr) 293 // 0 11110s xxxxxr 2 UInt(s) UInt(r) 294 // (s bits must not be all set) 295 // 296 // A pattern is constructed of size bits, where the least significant S+1 297 // bits are set. The pattern is rotated right by R, and repeated across a 298 // 32 or 64-bit value, depending on destination register width. 299 300 if (n == 1) { 301 DCHECK_NE(imm_s, 0x3fU); 302 uint64_t bits = BIT_MASK(imm_s + 1); 303 return RotateRight(bits, imm_r, 64); 304 } else { 305 DCHECK_NE((imm_s >> 1), 0x1fU); 306 for (unsigned width = 0x20; width >= 0x2; width >>= 1) { 307 if ((imm_s & width) == 0) { 308 unsigned mask = (unsigned)(width - 1); 309 DCHECK_NE((imm_s & mask), mask); 310 uint64_t bits = BIT_MASK((imm_s & mask) + 1); 311 return RepeatBitsAcrossReg(is_wide, RotateRight(bits, imm_r & mask, width), width); 312 } 313 } 314 } 315 return 0; 316 } 317 318 /** 319 * @brief Decode an 8-bit single point number encoded with EncodeImmSingle(). 320 */ 321 static float DecodeImmSingle(uint8_t small_float) { 322 int mantissa = (small_float & 0x0f) + 0x10; 323 int sign = ((small_float & 0x80) == 0) ? 1 : -1; 324 float signed_mantissa = static_cast<float>(sign*mantissa); 325 int exponent = (((small_float >> 4) & 0x7) + 4) & 0x7; 326 return signed_mantissa*static_cast<float>(1 << exponent)*0.0078125f; 327 } 328 329 static const char* cc_names[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 330 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"}; 331 /* 332 * Interpret a format string and build a string no longer than size 333 * See format key in assemble_arm64.cc. 334 */ 335 std::string Arm64Mir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) { 336 std::string buf; 337 const char* fmt_end = &fmt[strlen(fmt)]; 338 char tbuf[256]; 339 const char* name; 340 char nc; 341 while (fmt < fmt_end) { 342 int operand; 343 if (*fmt == '!') { 344 fmt++; 345 DCHECK_LT(fmt, fmt_end); 346 nc = *fmt++; 347 if (nc == '!') { 348 strcpy(tbuf, "!"); 349 } else { 350 DCHECK_LT(fmt, fmt_end); 351 DCHECK_LT(static_cast<unsigned>(nc-'0'), 4U); 352 operand = lir->operands[nc-'0']; 353 switch (*fmt++) { 354 case 'e': { 355 // Omit ", uxtw #0" in strings like "add w0, w1, w3, uxtw #0" and 356 // ", uxtx #0" in strings like "add x0, x1, x3, uxtx #0" 357 int omittable = ((IS_WIDE(lir->opcode)) ? EncodeExtend(kA64Uxtw, 0) : 358 EncodeExtend(kA64Uxtw, 0)); 359 if (LIKELY(operand == omittable)) { 360 strcpy(tbuf, ""); 361 } else { 362 DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf)); 363 } 364 } 365 break; 366 case 'o': 367 // Omit ", lsl #0" 368 if (LIKELY(operand == EncodeShift(kA64Lsl, 0))) { 369 strcpy(tbuf, ""); 370 } else { 371 DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf)); 372 } 373 break; 374 case 'B': 375 switch (operand) { 376 case kSY: 377 name = "sy"; 378 break; 379 case kST: 380 name = "st"; 381 break; 382 case kISH: 383 name = "ish"; 384 break; 385 case kISHST: 386 name = "ishst"; 387 break; 388 case kNSH: 389 name = "nsh"; 390 break; 391 case kNSHST: 392 name = "shst"; 393 break; 394 default: 395 name = "DecodeError2"; 396 break; 397 } 398 strcpy(tbuf, name); 399 break; 400 case 's': 401 snprintf(tbuf, arraysize(tbuf), "s%d", operand & RegStorage::kRegNumMask); 402 break; 403 case 'S': 404 snprintf(tbuf, arraysize(tbuf), "d%d", operand & RegStorage::kRegNumMask); 405 break; 406 case 'f': 407 snprintf(tbuf, arraysize(tbuf), "%c%d", (IS_FWIDE(lir->opcode)) ? 'd' : 's', 408 operand & RegStorage::kRegNumMask); 409 break; 410 case 'l': { 411 bool is_wide = IS_WIDE(lir->opcode); 412 uint64_t imm = DecodeLogicalImmediate(is_wide, operand); 413 snprintf(tbuf, arraysize(tbuf), "%" PRId64 " (%#" PRIx64 ")", imm, imm); 414 } 415 break; 416 case 'I': 417 snprintf(tbuf, arraysize(tbuf), "%f", DecodeImmSingle(operand)); 418 break; 419 case 'M': 420 if (LIKELY(operand == 0)) 421 strcpy(tbuf, ""); 422 else 423 snprintf(tbuf, arraysize(tbuf), ", lsl #%d", 16*operand); 424 break; 425 case 'd': 426 snprintf(tbuf, arraysize(tbuf), "%d", operand); 427 break; 428 case 'w': 429 if (LIKELY(operand != rwzr)) 430 snprintf(tbuf, arraysize(tbuf), "w%d", operand & RegStorage::kRegNumMask); 431 else 432 strcpy(tbuf, "wzr"); 433 break; 434 case 'W': 435 if (LIKELY(operand != rwsp)) 436 snprintf(tbuf, arraysize(tbuf), "w%d", operand & RegStorage::kRegNumMask); 437 else 438 strcpy(tbuf, "wsp"); 439 break; 440 case 'x': 441 if (LIKELY(operand != rxzr)) 442 snprintf(tbuf, arraysize(tbuf), "x%d", operand & RegStorage::kRegNumMask); 443 else 444 strcpy(tbuf, "xzr"); 445 break; 446 case 'X': 447 if (LIKELY(operand != rsp)) 448 snprintf(tbuf, arraysize(tbuf), "x%d", operand & RegStorage::kRegNumMask); 449 else 450 strcpy(tbuf, "sp"); 451 break; 452 case 'D': 453 snprintf(tbuf, arraysize(tbuf), "%d", operand*((IS_WIDE(lir->opcode)) ? 8 : 4)); 454 break; 455 case 'E': 456 snprintf(tbuf, arraysize(tbuf), "%d", operand*4); 457 break; 458 case 'F': 459 snprintf(tbuf, arraysize(tbuf), "%d", operand*2); 460 break; 461 case 'G': 462 if (LIKELY(operand == 0)) 463 strcpy(tbuf, ""); 464 else 465 strcpy(tbuf, (IS_WIDE(lir->opcode)) ? ", lsl #3" : ", lsl #2"); 466 break; 467 case 'c': 468 strcpy(tbuf, cc_names[operand]); 469 break; 470 case 't': 471 snprintf(tbuf, arraysize(tbuf), "0x%08" PRIxPTR " (L%p)", 472 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + (operand << 2), 473 lir->target); 474 break; 475 case 'r': { 476 bool is_wide = IS_WIDE(lir->opcode); 477 if (LIKELY(operand != rwzr && operand != rxzr)) { 478 snprintf(tbuf, arraysize(tbuf), "%c%d", (is_wide) ? 'x' : 'w', 479 operand & RegStorage::kRegNumMask); 480 } else { 481 strcpy(tbuf, (is_wide) ? "xzr" : "wzr"); 482 } 483 } 484 break; 485 case 'R': { 486 bool is_wide = IS_WIDE(lir->opcode); 487 if (LIKELY(operand != rwsp && operand != rsp)) { 488 snprintf(tbuf, arraysize(tbuf), "%c%d", (is_wide) ? 'x' : 'w', 489 operand & RegStorage::kRegNumMask); 490 } else { 491 strcpy(tbuf, (is_wide) ? "sp" : "wsp"); 492 } 493 } 494 break; 495 case 'p': 496 snprintf(tbuf, arraysize(tbuf), ".+%d (addr %#" PRIxPTR ")", 4*operand, 497 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4*operand); 498 break; 499 case 'T': 500 if (LIKELY(operand == 0)) 501 strcpy(tbuf, ""); 502 else if (operand == 1) 503 strcpy(tbuf, ", lsl #12"); 504 else 505 strcpy(tbuf, ", DecodeError3"); 506 break; 507 default: 508 strcpy(tbuf, "DecodeError1"); 509 break; 510 } 511 buf += tbuf; 512 } 513 } else { 514 buf += *fmt++; 515 } 516 } 517 return buf; 518 } 519 520 void Arm64Mir2Lir::DumpResourceMask(LIR* arm_lir, const ResourceMask& mask, const char* prefix) { 521 char buf[256]; 522 buf[0] = 0; 523 524 if (mask.Equals(kEncodeAll)) { 525 strcpy(buf, "all"); 526 } else { 527 char num[8]; 528 int i; 529 530 for (i = 0; i < kArm64RegEnd; i++) { 531 if (mask.HasBit(i)) { 532 snprintf(num, arraysize(num), "%d ", i); 533 strcat(buf, num); 534 } 535 } 536 537 if (mask.HasBit(ResourceMask::kCCode)) { 538 strcat(buf, "cc "); 539 } 540 if (mask.HasBit(ResourceMask::kFPStatus)) { 541 strcat(buf, "fpcc "); 542 } 543 544 /* Memory bits */ 545 if (arm_lir && (mask.HasBit(ResourceMask::kDalvikReg))) { 546 snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", 547 DECODE_ALIAS_INFO_REG(arm_lir->flags.alias_info), 548 DECODE_ALIAS_INFO_WIDE(arm_lir->flags.alias_info) ? "(+1)" : ""); 549 } 550 if (mask.HasBit(ResourceMask::kLiteral)) { 551 strcat(buf, "lit "); 552 } 553 554 if (mask.HasBit(ResourceMask::kHeapRef)) { 555 strcat(buf, "heap "); 556 } 557 if (mask.HasBit(ResourceMask::kMustNotAlias)) { 558 strcat(buf, "noalias "); 559 } 560 } 561 if (buf[0]) { 562 LOG(INFO) << prefix << ": " << buf; 563 } 564 } 565 566 bool Arm64Mir2Lir::IsUnconditionalBranch(LIR* lir) { 567 return (lir->opcode == kA64B1t); 568 } 569 570 RegisterClass Arm64Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { 571 if (UNLIKELY(is_volatile)) { 572 // On arm64, fp register load/store is atomic only for single bytes. 573 if (size != kSignedByte && size != kUnsignedByte) { 574 return (size == kReference) ? kRefReg : kCoreReg; 575 } 576 } 577 return RegClassBySize(size); 578 } 579 580 Arm64Mir2Lir::Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 581 : Mir2Lir(cu, mir_graph, arena) { 582 // Sanity check - make sure encoding map lines up. 583 for (int i = 0; i < kA64Last; i++) { 584 if (UNWIDE(Arm64Mir2Lir::EncodingMap[i].opcode) != i) { 585 LOG(FATAL) << "Encoding order for " << Arm64Mir2Lir::EncodingMap[i].name 586 << " is wrong: expecting " << i << ", seeing " 587 << static_cast<int>(Arm64Mir2Lir::EncodingMap[i].opcode); 588 } 589 } 590 } 591 592 Mir2Lir* Arm64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 593 ArenaAllocator* const arena) { 594 return new Arm64Mir2Lir(cu, mir_graph, arena); 595 } 596 597 void Arm64Mir2Lir::CompilerInitializeRegAlloc() { 598 reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs, core64_regs, sp_regs, dp_regs, 599 reserved_regs, reserved64_regs, core_temps, core64_temps, 600 sp_temps, dp_temps); 601 602 // Target-specific adjustments. 603 // Alias single precision float registers to corresponding double registers. 604 GrowableArray<RegisterInfo*>::Iterator fp_it(®_pool_->sp_regs_); 605 for (RegisterInfo* info = fp_it.Next(); info != nullptr; info = fp_it.Next()) { 606 int fp_reg_num = info->GetReg().GetRegNum(); 607 RegStorage dp_reg = RegStorage::FloatSolo64(fp_reg_num); 608 RegisterInfo* dp_reg_info = GetRegInfo(dp_reg); 609 // Double precision register's master storage should refer to itself. 610 DCHECK_EQ(dp_reg_info, dp_reg_info->Master()); 611 // Redirect single precision's master storage to master. 612 info->SetMaster(dp_reg_info); 613 // Singles should show a single 32-bit mask bit, at first referring to the low half. 614 DCHECK_EQ(info->StorageMask(), 0x1U); 615 } 616 617 // Alias 32bit W registers to corresponding 64bit X registers. 618 GrowableArray<RegisterInfo*>::Iterator w_it(®_pool_->core_regs_); 619 for (RegisterInfo* info = w_it.Next(); info != nullptr; info = w_it.Next()) { 620 int x_reg_num = info->GetReg().GetRegNum(); 621 RegStorage x_reg = RegStorage::Solo64(x_reg_num); 622 RegisterInfo* x_reg_info = GetRegInfo(x_reg); 623 // 64bit X register's master storage should refer to itself. 624 DCHECK_EQ(x_reg_info, x_reg_info->Master()); 625 // Redirect 32bit W master storage to 64bit X. 626 info->SetMaster(x_reg_info); 627 // 32bit W should show a single 32-bit mask bit, at first referring to the low half. 628 DCHECK_EQ(info->StorageMask(), 0x1U); 629 } 630 631 // Don't start allocating temps at r0/s0/d0 or you may clobber return regs in early-exit methods. 632 // TODO: adjust when we roll to hard float calling convention. 633 reg_pool_->next_core_reg_ = 2; 634 reg_pool_->next_sp_reg_ = 0; 635 reg_pool_->next_dp_reg_ = 0; 636 } 637 638 /* 639 * TUNING: is true leaf? Can't just use METHOD_IS_LEAF to determine as some 640 * instructions might call out to C/assembly helper functions. Until 641 * machinery is in place, always spill lr. 642 */ 643 644 void Arm64Mir2Lir::AdjustSpillMask() { 645 core_spill_mask_ |= (1 << rs_xLR.GetRegNum()); 646 num_core_spills_++; 647 } 648 649 /* Clobber all regs that might be used by an external C call */ 650 void Arm64Mir2Lir::ClobberCallerSave() { 651 Clobber(rs_x0); 652 Clobber(rs_x1); 653 Clobber(rs_x2); 654 Clobber(rs_x3); 655 Clobber(rs_x4); 656 Clobber(rs_x5); 657 Clobber(rs_x6); 658 Clobber(rs_x7); 659 Clobber(rs_x8); 660 Clobber(rs_x9); 661 Clobber(rs_x10); 662 Clobber(rs_x11); 663 Clobber(rs_x12); 664 Clobber(rs_x13); 665 Clobber(rs_x14); 666 Clobber(rs_x15); 667 Clobber(rs_x16); 668 Clobber(rs_x17); 669 Clobber(rs_x30); 670 671 Clobber(rs_f0); 672 Clobber(rs_f1); 673 Clobber(rs_f2); 674 Clobber(rs_f3); 675 Clobber(rs_f4); 676 Clobber(rs_f5); 677 Clobber(rs_f6); 678 Clobber(rs_f7); 679 Clobber(rs_f16); 680 Clobber(rs_f17); 681 Clobber(rs_f18); 682 Clobber(rs_f19); 683 Clobber(rs_f20); 684 Clobber(rs_f21); 685 Clobber(rs_f22); 686 Clobber(rs_f23); 687 Clobber(rs_f24); 688 Clobber(rs_f25); 689 Clobber(rs_f26); 690 Clobber(rs_f27); 691 Clobber(rs_f28); 692 Clobber(rs_f29); 693 Clobber(rs_f30); 694 Clobber(rs_f31); 695 } 696 697 RegLocation Arm64Mir2Lir::GetReturnWideAlt() { 698 RegLocation res = LocCReturnWide(); 699 res.reg.SetReg(rx2); 700 res.reg.SetHighReg(rx3); 701 Clobber(rs_x2); 702 Clobber(rs_x3); 703 MarkInUse(rs_x2); 704 MarkInUse(rs_x3); 705 MarkWide(res.reg); 706 return res; 707 } 708 709 RegLocation Arm64Mir2Lir::GetReturnAlt() { 710 RegLocation res = LocCReturn(); 711 res.reg.SetReg(rx1); 712 Clobber(rs_x1); 713 MarkInUse(rs_x1); 714 return res; 715 } 716 717 /* To be used when explicitly managing register use */ 718 void Arm64Mir2Lir::LockCallTemps() { 719 // TODO: needs cleanup. 720 LockTemp(rs_x0); 721 LockTemp(rs_x1); 722 LockTemp(rs_x2); 723 LockTemp(rs_x3); 724 LockTemp(rs_x4); 725 LockTemp(rs_x5); 726 LockTemp(rs_x6); 727 LockTemp(rs_x7); 728 LockTemp(rs_f0); 729 LockTemp(rs_f1); 730 LockTemp(rs_f2); 731 LockTemp(rs_f3); 732 LockTemp(rs_f4); 733 LockTemp(rs_f5); 734 LockTemp(rs_f6); 735 LockTemp(rs_f7); 736 } 737 738 /* To be used when explicitly managing register use */ 739 void Arm64Mir2Lir::FreeCallTemps() { 740 // TODO: needs cleanup. 741 FreeTemp(rs_x0); 742 FreeTemp(rs_x1); 743 FreeTemp(rs_x2); 744 FreeTemp(rs_x3); 745 FreeTemp(rs_x4); 746 FreeTemp(rs_x5); 747 FreeTemp(rs_x6); 748 FreeTemp(rs_x7); 749 FreeTemp(rs_f0); 750 FreeTemp(rs_f1); 751 FreeTemp(rs_f2); 752 FreeTemp(rs_f3); 753 FreeTemp(rs_f4); 754 FreeTemp(rs_f5); 755 FreeTemp(rs_f6); 756 FreeTemp(rs_f7); 757 FreeTemp(TargetReg(kHiddenArg)); 758 } 759 760 RegStorage Arm64Mir2Lir::LoadHelper(QuickEntrypointEnum trampoline) { 761 // TODO(Arm64): use LoadWordDisp instead. 762 // e.g. LoadWordDisp(rs_rA64_SELF, offset.Int32Value(), rs_rA64_LR); 763 LoadBaseDisp(rs_xSELF, GetThreadOffset<8>(trampoline).Int32Value(), rs_xLR, k64, kNotVolatile); 764 return rs_xLR; 765 } 766 767 LIR* Arm64Mir2Lir::CheckSuspendUsingLoad() { 768 RegStorage tmp = rs_x0; 769 LoadWordDisp(rs_xSELF, Thread::ThreadSuspendTriggerOffset<8>().Int32Value(), tmp); 770 LIR* load2 = LoadWordDisp(tmp, 0, tmp); 771 return load2; 772 } 773 774 uint64_t Arm64Mir2Lir::GetTargetInstFlags(int opcode) { 775 DCHECK(!IsPseudoLirOp(opcode)); 776 return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].flags; 777 } 778 779 const char* Arm64Mir2Lir::GetTargetInstName(int opcode) { 780 DCHECK(!IsPseudoLirOp(opcode)); 781 return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].name; 782 } 783 784 const char* Arm64Mir2Lir::GetTargetInstFmt(int opcode) { 785 DCHECK(!IsPseudoLirOp(opcode)); 786 return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].fmt; 787 } 788 789 RegStorage Arm64Mir2Lir::InToRegStorageArm64Mapper::GetNextReg(bool is_double_or_float, 790 bool is_wide, 791 bool is_ref) { 792 const RegStorage coreArgMappingToPhysicalReg[] = 793 {rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7}; 794 const int coreArgMappingToPhysicalRegSize = 795 sizeof(coreArgMappingToPhysicalReg) / sizeof(RegStorage); 796 const RegStorage fpArgMappingToPhysicalReg[] = 797 {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7}; 798 const int fpArgMappingToPhysicalRegSize = 799 sizeof(fpArgMappingToPhysicalReg) / sizeof(RegStorage); 800 801 RegStorage result = RegStorage::InvalidReg(); 802 if (is_double_or_float) { 803 if (cur_fp_reg_ < fpArgMappingToPhysicalRegSize) { 804 DCHECK(!is_ref); 805 result = fpArgMappingToPhysicalReg[cur_fp_reg_++]; 806 if (result.Valid()) { 807 // TODO: switching between widths remains a bit ugly. Better way? 808 int res_reg = result.GetReg(); 809 result = is_wide ? RegStorage::FloatSolo64(res_reg) : RegStorage::FloatSolo32(res_reg); 810 } 811 } 812 } else { 813 if (cur_core_reg_ < coreArgMappingToPhysicalRegSize) { 814 result = coreArgMappingToPhysicalReg[cur_core_reg_++]; 815 if (result.Valid()) { 816 // TODO: switching between widths remains a bit ugly. Better way? 817 int res_reg = result.GetReg(); 818 DCHECK(!(is_wide && is_ref)); 819 result = (is_wide || is_ref) ? RegStorage::Solo64(res_reg) : RegStorage::Solo32(res_reg); 820 } 821 } 822 } 823 return result; 824 } 825 826 RegStorage Arm64Mir2Lir::InToRegStorageMapping::Get(int in_position) { 827 DCHECK(IsInitialized()); 828 auto res = mapping_.find(in_position); 829 return res != mapping_.end() ? res->second : RegStorage::InvalidReg(); 830 } 831 832 void Arm64Mir2Lir::InToRegStorageMapping::Initialize(RegLocation* arg_locs, int count, 833 InToRegStorageMapper* mapper) { 834 DCHECK(mapper != nullptr); 835 max_mapped_in_ = -1; 836 is_there_stack_mapped_ = false; 837 for (int in_position = 0; in_position < count; in_position++) { 838 RegStorage reg = mapper->GetNextReg(arg_locs[in_position].fp, 839 arg_locs[in_position].wide, 840 arg_locs[in_position].ref); 841 if (reg.Valid()) { 842 mapping_[in_position] = reg; 843 if (arg_locs[in_position].wide) { 844 // We covered 2 args, so skip the next one 845 in_position++; 846 } 847 max_mapped_in_ = std::max(max_mapped_in_, in_position); 848 } else { 849 is_there_stack_mapped_ = true; 850 } 851 } 852 initialized_ = true; 853 } 854 855 856 // Deprecate. Use the new mechanism. 857 // TODO(Arm64): reuse info in QuickArgumentVisitor? 858 static RegStorage GetArgPhysicalReg(RegLocation* loc, int* num_gpr_used, int* num_fpr_used, 859 OpSize* op_size) { 860 if (loc->fp) { 861 int n = *num_fpr_used; 862 if (n < 8) { 863 *num_fpr_used = n + 1; 864 RegStorage::RegStorageKind reg_kind; 865 if (loc->wide) { 866 *op_size = kDouble; 867 reg_kind = RegStorage::k64BitSolo; 868 } else { 869 *op_size = kSingle; 870 reg_kind = RegStorage::k32BitSolo; 871 } 872 return RegStorage(RegStorage::kValid | reg_kind | RegStorage::kFloatingPoint | n); 873 } 874 } else { 875 int n = *num_gpr_used; 876 if (n < 8) { 877 *num_gpr_used = n + 1; 878 if (loc->wide || loc->ref) { 879 *op_size = k64; 880 return RegStorage::Solo64(n); 881 } else { 882 *op_size = k32; 883 return RegStorage::Solo32(n); 884 } 885 } 886 } 887 *op_size = kWord; 888 return RegStorage::InvalidReg(); 889 } 890 891 RegStorage Arm64Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { 892 if (!in_to_reg_storage_mapping_.IsInitialized()) { 893 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 894 RegLocation* arg_locs = &mir_graph_->reg_location_[start_vreg]; 895 896 InToRegStorageArm64Mapper mapper; 897 in_to_reg_storage_mapping_.Initialize(arg_locs, cu_->num_ins, &mapper); 898 } 899 return in_to_reg_storage_mapping_.Get(arg_num); 900 } 901 902 903 /* 904 * If there are any ins passed in registers that have not been promoted 905 * to a callee-save register, flush them to the frame. Perform initial 906 * assignment of promoted arguments. 907 * 908 * ArgLocs is an array of location records describing the incoming arguments 909 * with one location record per word of argument. 910 */ 911 void Arm64Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) { 912 int num_gpr_used = 1; 913 int num_fpr_used = 0; 914 915 /* 916 * Dummy up a RegLocation for the incoming StackReference<mirror::ArtMethod> 917 * It will attempt to keep kArg0 live (or copy it to home location 918 * if promoted). 919 */ 920 RegLocation rl_src = rl_method; 921 rl_src.location = kLocPhysReg; 922 rl_src.reg = TargetReg(kArg0, kRef); 923 rl_src.home = false; 924 MarkLive(rl_src); 925 StoreValue(rl_method, rl_src); 926 // If Method* has been promoted, explicitly flush 927 if (rl_method.location == kLocPhysReg) { 928 StoreRefDisp(TargetPtrReg(kSp), 0, rl_src.reg, kNotVolatile); 929 } 930 931 if (cu_->num_ins == 0) { 932 return; 933 } 934 935 // Handle dalvik registers. 936 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 937 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 938 for (int i = 0; i < cu_->num_ins; i++) { 939 RegLocation* t_loc = &ArgLocs[i]; 940 OpSize op_size; 941 RegStorage reg = GetArgPhysicalReg(t_loc, &num_gpr_used, &num_fpr_used, &op_size); 942 943 if (reg.Valid()) { 944 // If arriving in register. 945 946 // We have already updated the arg location with promoted info 947 // so we can be based on it. 948 if (t_loc->location == kLocPhysReg) { 949 // Just copy it. 950 OpRegCopy(t_loc->reg, reg); 951 } else { 952 // Needs flush. 953 if (t_loc->ref) { 954 StoreRefDisp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), reg, kNotVolatile); 955 } else { 956 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), reg, t_loc->wide ? k64 : k32, 957 kNotVolatile); 958 } 959 } 960 } else { 961 // If arriving in frame & promoted. 962 if (t_loc->location == kLocPhysReg) { 963 if (t_loc->ref) { 964 LoadRefDisp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), t_loc->reg, kNotVolatile); 965 } else { 966 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), t_loc->reg, 967 t_loc->wide ? k64 : k32, kNotVolatile); 968 } 969 } 970 } 971 if (t_loc->wide) { 972 // Increment i to skip the next one. 973 i++; 974 } 975 // if ((v_map->core_location == kLocPhysReg) && !t_loc->fp) { 976 // OpRegCopy(RegStorage::Solo32(v_map->core_reg), reg); 977 // } else if ((v_map->fp_location == kLocPhysReg) && t_loc->fp) { 978 // OpRegCopy(RegStorage::Solo32(v_map->fp_reg), reg); 979 // } else { 980 // StoreBaseDisp(TargetReg(kSp), SRegOffset(start_vreg + i), reg, op_size, kNotVolatile); 981 // if (reg.Is64Bit()) { 982 // if (SRegOffset(start_vreg + i) + 4 != SRegOffset(start_vreg + i + 1)) { 983 // LOG(FATAL) << "64 bit value stored in non-consecutive 4 bytes slots"; 984 // } 985 // i += 1; 986 // } 987 // } 988 // } else { 989 // // If arriving in frame & promoted 990 // if (v_map->core_location == kLocPhysReg) { 991 // LoadWordDisp(TargetReg(kSp), SRegOffset(start_vreg + i), 992 // RegStorage::Solo32(v_map->core_reg)); 993 // } 994 // if (v_map->fp_location == kLocPhysReg) { 995 // LoadWordDisp(TargetReg(kSp), SRegOffset(start_vreg + i), RegStorage::Solo32(v_map->fp_reg)); 996 // } 997 } 998 } 999 1000 /* 1001 * Load up to 5 arguments, the first three of which will be in 1002 * kArg1 .. kArg3. On entry kArg0 contains the current method pointer, 1003 * and as part of the load sequence, it must be replaced with 1004 * the target method pointer. 1005 */ 1006 int Arm64Mir2Lir::GenDalvikArgsNoRange(CallInfo* info, 1007 int call_state, LIR** pcrLabel, NextCallInsn next_call_insn, 1008 const MethodReference& target_method, 1009 uint32_t vtable_idx, uintptr_t direct_code, 1010 uintptr_t direct_method, InvokeType type, bool skip_this) { 1011 return GenDalvikArgsRange(info, 1012 call_state, pcrLabel, next_call_insn, 1013 target_method, 1014 vtable_idx, direct_code, 1015 direct_method, type, skip_this); 1016 } 1017 1018 /* 1019 * May have 0+ arguments (also used for jumbo). Note that 1020 * source virtual registers may be in physical registers, so may 1021 * need to be flushed to home location before copying. This 1022 * applies to arg3 and above (see below). 1023 * 1024 * FIXME: update comments. 1025 * 1026 * Two general strategies: 1027 * If < 20 arguments 1028 * Pass args 3-18 using vldm/vstm block copy 1029 * Pass arg0, arg1 & arg2 in kArg1-kArg3 1030 * If 20+ arguments 1031 * Pass args arg19+ using memcpy block copy 1032 * Pass arg0, arg1 & arg2 in kArg1-kArg3 1033 * 1034 */ 1035 int Arm64Mir2Lir::GenDalvikArgsRange(CallInfo* info, int call_state, 1036 LIR** pcrLabel, NextCallInsn next_call_insn, 1037 const MethodReference& target_method, 1038 uint32_t vtable_idx, uintptr_t direct_code, 1039 uintptr_t direct_method, InvokeType type, bool skip_this) { 1040 /* If no arguments, just return */ 1041 if (info->num_arg_words == 0) 1042 return call_state; 1043 1044 const int start_index = skip_this ? 1 : 0; 1045 1046 InToRegStorageArm64Mapper mapper; 1047 InToRegStorageMapping in_to_reg_storage_mapping; 1048 in_to_reg_storage_mapping.Initialize(info->args, info->num_arg_words, &mapper); 1049 const int last_mapped_in = in_to_reg_storage_mapping.GetMaxMappedIn(); 1050 int regs_left_to_pass_via_stack = info->num_arg_words - (last_mapped_in + 1); 1051 1052 // First of all, check whether it makes sense to use bulk copying. 1053 // Bulk copying is done only for the range case. 1054 // TODO: make a constant instead of 2 1055 if (info->is_range && regs_left_to_pass_via_stack >= 2) { 1056 // Scan the rest of the args - if in phys_reg flush to memory 1057 for (int next_arg = last_mapped_in + 1; next_arg < info->num_arg_words;) { 1058 RegLocation loc = info->args[next_arg]; 1059 if (loc.wide) { 1060 loc = UpdateLocWide(loc); 1061 if (loc.location == kLocPhysReg) { 1062 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1063 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile); 1064 } 1065 next_arg += 2; 1066 } else { 1067 loc = UpdateLoc(loc); 1068 if (loc.location == kLocPhysReg) { 1069 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1070 if (loc.ref) { 1071 StoreRefDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, kNotVolatile); 1072 } else { 1073 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k32, 1074 kNotVolatile); 1075 } 1076 } 1077 next_arg++; 1078 } 1079 } 1080 1081 // Logic below assumes that Method pointer is at offset zero from SP. 1082 DCHECK_EQ(VRegOffset(static_cast<int>(kVRegMethodPtrBaseReg)), 0); 1083 1084 // The rest can be copied together 1085 int start_offset = SRegOffset(info->args[last_mapped_in + 1].s_reg_low); 1086 int outs_offset = StackVisitor::GetOutVROffset(last_mapped_in + 1, 1087 cu_->instruction_set); 1088 1089 int current_src_offset = start_offset; 1090 int current_dest_offset = outs_offset; 1091 1092 // Only davik regs are accessed in this loop; no next_call_insn() calls. 1093 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1094 while (regs_left_to_pass_via_stack > 0) { 1095 /* 1096 * TODO: Improve by adding block copy for large number of arguments. This 1097 * should be done, if possible, as a target-depending helper. For now, just 1098 * copy a Dalvik vreg at a time. 1099 */ 1100 // Moving 32-bits via general purpose register. 1101 size_t bytes_to_move = sizeof(uint32_t); 1102 1103 // Instead of allocating a new temp, simply reuse one of the registers being used 1104 // for argument passing. 1105 RegStorage temp = TargetReg(kArg3, kNotWide); 1106 1107 // Now load the argument VR and store to the outs. 1108 Load32Disp(TargetPtrReg(kSp), current_src_offset, temp); 1109 Store32Disp(TargetPtrReg(kSp), current_dest_offset, temp); 1110 1111 current_src_offset += bytes_to_move; 1112 current_dest_offset += bytes_to_move; 1113 regs_left_to_pass_via_stack -= (bytes_to_move >> 2); 1114 } 1115 DCHECK_EQ(regs_left_to_pass_via_stack, 0); 1116 } 1117 1118 // Now handle rest not registers if they are 1119 if (in_to_reg_storage_mapping.IsThereStackMapped()) { 1120 RegStorage regWide = TargetReg(kArg3, kWide); 1121 for (int i = start_index; i <= last_mapped_in + regs_left_to_pass_via_stack; i++) { 1122 RegLocation rl_arg = info->args[i]; 1123 rl_arg = UpdateRawLoc(rl_arg); 1124 RegStorage reg = in_to_reg_storage_mapping.Get(i); 1125 if (!reg.Valid()) { 1126 int out_offset = StackVisitor::GetOutVROffset(i, cu_->instruction_set); 1127 1128 { 1129 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1130 if (rl_arg.wide) { 1131 if (rl_arg.location == kLocPhysReg) { 1132 StoreBaseDisp(TargetPtrReg(kSp), out_offset, rl_arg.reg, k64, kNotVolatile); 1133 } else { 1134 LoadValueDirectWideFixed(rl_arg, regWide); 1135 StoreBaseDisp(TargetPtrReg(kSp), out_offset, regWide, k64, kNotVolatile); 1136 } 1137 } else { 1138 if (rl_arg.location == kLocPhysReg) { 1139 if (rl_arg.ref) { 1140 StoreRefDisp(TargetPtrReg(kSp), out_offset, rl_arg.reg, kNotVolatile); 1141 } else { 1142 StoreBaseDisp(TargetPtrReg(kSp), out_offset, rl_arg.reg, k32, kNotVolatile); 1143 } 1144 } else { 1145 if (rl_arg.ref) { 1146 RegStorage regSingle = TargetReg(kArg2, kRef); 1147 LoadValueDirectFixed(rl_arg, regSingle); 1148 StoreRefDisp(TargetPtrReg(kSp), out_offset, regSingle, kNotVolatile); 1149 } else { 1150 RegStorage regSingle = TargetReg(kArg2, kNotWide); 1151 LoadValueDirectFixed(rl_arg, regSingle); 1152 StoreBaseDisp(TargetPtrReg(kSp), out_offset, regSingle, k32, kNotVolatile); 1153 } 1154 } 1155 } 1156 } 1157 call_state = next_call_insn(cu_, info, call_state, target_method, 1158 vtable_idx, direct_code, direct_method, type); 1159 } 1160 if (rl_arg.wide) { 1161 i++; 1162 } 1163 } 1164 } 1165 1166 // Finish with mapped registers 1167 for (int i = start_index; i <= last_mapped_in; i++) { 1168 RegLocation rl_arg = info->args[i]; 1169 rl_arg = UpdateRawLoc(rl_arg); 1170 RegStorage reg = in_to_reg_storage_mapping.Get(i); 1171 if (reg.Valid()) { 1172 if (rl_arg.wide) { 1173 LoadValueDirectWideFixed(rl_arg, reg); 1174 } else { 1175 LoadValueDirectFixed(rl_arg, reg); 1176 } 1177 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 1178 direct_code, direct_method, type); 1179 } 1180 if (rl_arg.wide) { 1181 i++; 1182 } 1183 } 1184 1185 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 1186 direct_code, direct_method, type); 1187 if (pcrLabel) { 1188 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 1189 *pcrLabel = GenExplicitNullCheck(TargetReg(kArg1, kRef), info->opt_flags); 1190 } else { 1191 *pcrLabel = nullptr; 1192 // In lieu of generating a check for kArg1 being null, we need to 1193 // perform a load when doing implicit checks. 1194 RegStorage tmp = AllocTemp(); 1195 Load32Disp(TargetReg(kArg1, kRef), 0, tmp); 1196 MarkPossibleNullPointerException(info->opt_flags); 1197 FreeTemp(tmp); 1198 } 1199 } 1200 return call_state; 1201 } 1202 1203 } // namespace art 1204
