| /external/clang/test/CodeGenCXX/ |
| debug-info-byval.cpp | 5 class DAG {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.h | 27 const ScheduleDAG *DAG;
37 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_),
57 const ScheduleDAG &DAG;
78 PPCHazardRecognizer970(const ScheduleDAG &DAG);
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| /external/llvm/include/llvm/CodeGen/ |
| ScoreboardHazardRecognizer.h | 95 const ScheduleDAG *DAG;
108 const ScheduleDAG *DAG,
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| SelectionDAG.h | 1 //===-- llvm/CodeGen/SelectionDAG.h - InstSelection DAG ---------*- C++ -*-===//
154 void checkForCycles(const SelectionDAG *DAG, bool force = false);
157 /// in a low-level Data Dependence DAG representation suitable for instruction
158 /// selection. This DAG is constructed as the first step of instruction
178 /// Root - The root of the entire DAG.
181 /// AllNodes - A linked list of nodes in the current DAG.
209 /// the DAG can optionally implement this interface. This allows the clients
212 /// A DAGUpdateListener automatically registers itself with DAG when it is
216 SelectionDAG &DAG;
219 : Next(D.UpdateListeners), DAG(D)
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| MachineScheduler.h | 18 // scheduled. Targets can override the DAG builder and scheduler without
26 // The default scheduler, ScheduleDAGMILive, builds the DAG and drives list
28 // intervals. Most targets don't need to override the DAG builder and list
38 // The DAG builder can also be customized in a sense by adding DAG mutations
39 // that will run after DAG building and before list scheduling. DAG mutations
45 // ScheduleDAGMI *DAG = new ScheduleDAGMI(C, CustomStrategy(C));
46 // DAG->addMutation(new CustomDependencies(DAG->TII, DAG->TRI))
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 34 /// the DAG and must be handled explicitly by schedulers.
39 SelectionDAG *DAG; // DAG of the current basic block
51 void Run(SelectionDAG *dag, MachineBasicBlock *bb);
82 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
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| LegalizeTypes.h | 1 //===-- LegalizeTypes.h - DAG Type Legalizer class definition ---*- C++ -*-===//
36 SelectionDAG &DAG;
67 return TLI.getTypeAction(*DAG.getContext(), VT);
72 return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
76 return TLI.getSetCCResultType(*DAG.getContext(), VT);
122 explicit DAGTypeLegalizer(SelectionDAG &dag)
123 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
130 /// top-down traversal of the dag, legalizing types as it goes. Return
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| LegalizeDAG.cpp | 54 SelectionDAG &DAG;
63 return TLI.getSetCCResultType(*DAG.getContext(), VT);
69 explicit SelectionDAGLegalize(SelectionDAG &DAG);
164 DAG.RemoveDeadNode(N);
170 DAG.ReplaceAllUsesWith(Old, New);
174 DAG.ReplaceAllUsesWith(Old, New);
178 DAG.ReplaceAllUsesWith(Old, New);
199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
213 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
216 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
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| LegalizeVectorOps.cpp | 36 SelectionDAG& DAG;
127 /// \brief Begin legalizer the vector operations in the DAG.
129 VectorLegalizer(SelectionDAG& dag) :
130 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
136 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
137 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
159 DAG.AssignTopologicalOrder();
160 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin()
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| SelectionDAGBuilder.h | 1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------*- C++ -*---===//
344 /// implying one could not create a DAG Combine to move the callinst.
495 SelectionDAG &DAG;
533 /// no subsequent DAG nodes should be created.
539 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
541 : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
542 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
565 /// getRoot - Return the current virtual root of the Selection DAG,
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| TargetLowering.cpp | 48 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
50 const Function *F = DAG.getMachineFunction().getFunction();
86 TargetLowering::makeLibCall(SelectionDAG &DAG,
98 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
103 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
105 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
106 TargetLowering::CallLoweringInfo CLI(DAG);
107 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
117 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
201 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/
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| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.h | 29 const ScheduleDAGMILive *DAG;
71 DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
76 void initialize(ScheduleDAGMI *dag) override;
|
| R600ISelLowering.cpp | 1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
11 /// \brief Custom DAG lowering for R600
564 // Custom DAG Lowering Operations
567 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
568 MachineFunction &MF = DAG.getMachineFunction();
571 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
572 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
573 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
574 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
576 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
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| SIISelLowering.cpp | 1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
11 /// \brief Custom DAG lowering for SI
288 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
291 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
292 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
294 SDValue BasePtr = DAG.getCopyFromReg(Chain, DL,
296 SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
297 DAG.getConstant(Offset, MVT::i64));
298 return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
309 SDLoc DL, SelectionDAG &DAG,
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
10 // Most of the DAG lowering is handled in AMDGPUISelLowering.cpp. This file is
258 // Custom DAG Lowering Operations
261 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
264 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
265 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
266 case ISD::LOAD: return LowerLOAD(Op, DAG);
267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
268 case ISD::AND: return Loweri1ContextSwitch(Op, DAG, ISD::AND);
275 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.h | 103 /// Perform platform-specific DAG postprocessing.
134 VLIWMachineScheduler *DAG;
156 DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"),
167 void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) {
168 DAG = dag;
191 VLIWMachineScheduler *DAG;
207 : DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"),
210 virtual void initialize(ScheduleDAGMI *dag) override;
|
| HexagonISelLowering.cpp | 1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
11 // into a selection DAG.
289 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
301 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
304 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
305 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
319 SDLoc dl, SelectionDAG &DAG) const {
325 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
326 getTargetMachine(), RVLocs, *DAG.getContext());
338 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag)
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
10 // Most of the DAG lowering is handled in AMDGPUISelLowering.cpp. This file is
258 // Custom DAG Lowering Operations
261 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
264 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
265 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
266 case ISD::LOAD: return LowerLOAD(Op, DAG);
267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
268 case ISD::AND: return Loweri1ContextSwitch(Op, DAG, ISD::AND);
275 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass
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| /external/llvm/lib/Target/Mips/ |
| Mips16ISelLowering.cpp | 1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
424 SelectionDAG &DAG = CLI.DAG;
425 MachineFunction &MF = DAG.getMachineFunction();
501 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy());
503 JumpTarget = getAddrGlobal(S, JumpTarget.getValueType(), DAG,
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| MipsSEISelLowering.cpp | 1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
357 SelectionDAG &DAG) const {
359 case ISD::LOAD: return lowerLOAD(Op, DAG);
360 case ISD::STORE: return lowerSTORE(Op, DAG);
361 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
362 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
363 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
364 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
365 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
366 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
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| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
185 SelectionDAG &DAG) const {
189 case ISD::SRA: return LowerShifts(Op, DAG);
190 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
191 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
192 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
193 case ISD::SETCC: return LowerSETCC(Op, DAG);
194 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
195 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
196 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
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| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
519 /// being extended to be a GPR32, but the incoming DAG might be acting on a
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| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
177 // We have target-specific dag combine patterns for the following nodes:
206 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
209 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
210 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
211 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
212 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
213 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
214 case ISD::LOAD: return LowerLOAD(Op, DAG);
215 case ISD::STORE: return LowerSTORE(Op, DAG);
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| /external/llvm/lib/CodeGen/ |
| MachineScheduler.cpp | 76 // DAG subtrees must have at least this many nodes.
291 /// consistent with the DAG builder, which traverses the interior of the
294 /// This design avoids exposing scheduling boundaries to the DAG builder,
295 /// simplifying the DAG builder's support for "special" target instructions.
365 /// handle calls, the DAG builder needs to be modified to create register
403 // boundary at the bottom of the region. The DAG does not include RegionEnd,
644 // Build the DAG.
654 // Initialize the strategy before modifying the DAG.
662 // Initialize ready queues now that the DAG and priority data are finalized.
692 // Notify the scheduling strategy before updating the DAG
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 10 // selection DAG.
255 // We have some custom DAG combine patterns for these nodes
485 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
488 Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
489 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op);
653 SelectionDAG &DAG = CLI.DAG;
670 MachineFunction &MF = DAG.getMachineFunction();
675 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(uniqueCallSite, true)
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