| /external/llvm/lib/Target/R600/ |
| SIMachineFunctionInfo.h | 33 int Lane;
34 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
35 SpilledReg() : VGPR(0), Lane(-1) { }
36 bool hasLane() { return Lane != -1;}
49 /// \returns The lane to be used for storing the first register.
52 void addSpilledReg(unsigned FrameIndex, unsigned Reg, int Lane = -1);
|
| SIISelLowering.cpp | [all...] |
| SIInstrInfo.cpp | 203 unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MF);
208 .addImm(Lane);
209 MFI->SpillTracker.addSpilledReg(FrameIndex, TgtReg, Lane);
335 .addImm(Spill.Lane + i);
358 .addImm(Spill.Lane + i);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 67 unsigned Reg, unsigned Lane,
73 unsigned DReg, unsigned Lane,
88 DebugLoc DL, unsigned DReg, unsigned Lane,
428 unsigned Reg, unsigned Lane, bool QPR) {
437 .addImm(Lane));
442 // Creates a SPR register from a DPR by copying the value in lane 0.
447 unsigned DReg, unsigned Lane,
454 .addReg(DReg, 0, Lane);
498 DebugLoc DL, unsigned DReg, unsigned Lane,
507 .addImm(Lane);
[all...] |
| ARMExpandPseudoInsts.cpp | 93 // For quad-register load-lane and store-lane pseudo instructors, the
95 // OddDblSpc depending on the lane number operand.
112 uint8_t RegElts; // elements per D register; used for lane ops
511 // The lane operand is always the 3rd from last operand, before the 2
513 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
515 // Adjust the lane and spacing as needed for Q registers.
516 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
517 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
519 Lane -= RegElts
[all...] |
| ARMISelDAGToDAG.cpp | 230 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
[all...] |
| ARMBaseInstrInfo.cpp | 67 bool HasLane; // True if instruction has an extra "lane" operand.
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| SLPVectorizer.cpp | 543 Scalar(S), User(U), Lane(L){};
548 // Which lane does the scalar belong to.
549 int Lane;
604 // For each lane:
605 for (int Lane = 0, LE = Entry->Scalars.size(); Lane != LE; ++Lane) {
606 Value *Scalar = Entry->Scalars[Lane];
632 DEBUG(dbgs() << "SLP: Need to extract:" << *U << " from lane " <<
633 Lane << " from " << *Scalar << ".\n")
[all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
